Jean-Marc Daveau

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 10

Top Topics

Graph Partitioning

Spectral Density

Top Venues

Publications

Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
Formal Resilience Metric Characterization in Complex Digital Systems. ETS (2024)
Esther Goudet, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. J. Electron. Test. 40 (3) (2024)
Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
Formal Temporal Characterization of Register Vulnerability in Digital Circuits. ISVLSI (2023)
Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. LATS (2023)
Tiziano Fiorucci, Giorgio Di Natale, Jean-Marc Daveau, Philippe Roche
Software Product Reliability Based on Basic Block Metrics Recomposition. IOLTS (2022)
Tiziano Fiorucci, Jean-Marc Daveau, Giorgio Di Natale, Philippe Roche
Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems. IOLTS (2021)
Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT (2021)
Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. IEEE J. Solid State Circuits 53 (7) (2018)
Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran
A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. ESSCIRC (2017)
Fady Abouzeid, Christophe Bernicot, Sylvain Clerc, Jean-Marc Daveau, Gilles Gasiot, Daniel Noblet, Dimitri Soussan, Philippe Roche
-A53 using static biasing-anticipation. ESSCIRC (2016)
Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED (2015)
Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC (2015)
Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid, Sylvain Clerc, Lirida A. B. Naviner, Philippe Roche
Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS (2015)
Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC (2015)
Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
Partial triplication of a SPARC-V8 microprocessor using fault injection. LASCAS (2015)
Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. IOLTS (2011)
Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
Fast reliability analysis of combinatorial logic circuits using conditional probabilities. Microelectron. Reliab. 50 (9-11) (2010)
Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. ICECS (2010)
Oscar Bailan, Umberto Rossi, Anne Wantens, Jean-Marc Daveau, Salvatore Nappi, Philippe Roche
Verification of soft error detection mechanism through fault injection on hardware emulation platform. DSN Workshops (2010)
Philippe Roche, Mark Lysinger, Gilles Gasiot, Jean-Marc Daveau, Mehdi Zamanian, Pierre Dautriche
Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS. IOLTS (2008)
Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana
A retargetable register allocation framework for embedded processors. LCTES (2004)
Valérie Bertin, Jean-Marc Daveau, Philippe Guillaume, Thierry Lepley, Denis Pilat, Claire Richard, Miguel Santana, Thomas Thery
FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors. EMSOFT (2002)
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau
Automating the Design of SOCs Using Cores. IEEE Des. Test Comput. 18 (5) (2001)
Fabiano Hessel, Pascal Coste, Philippe Le Marrec, Nacer-Eddine Zergainoh, Gabriela Nicolescu, Jean-Marc Daveau, Ahmed Amine Jerraya
Interlanguage Communication Synthesis for Heterogeneous Specifications. Des. Autom. Embed. Syst. 5 (3-4) (2000)
Fabiano Hessel, Philippe Coste, P. LeMarrec, Nacer-Eddine Zergainoh, Jean-Marc Daveau, Ahmed Amine Jerraya
Communication Interface Synthesis for Multilanguage Specifications. IEEE International Workshop on Rapid System Prototyping (1999)
Jean-Marc Daveau, Gilberto Fernandes Marchioro, Ahmed Amine Jerraya
Hardware/software co-design of an ATM network interface card: a case study. CODES (1998)
Mohamed Abid, Tarek Ben Ismail, Adel Changuel, Carlos A. Valderrama, Mohamed Romdhani, Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya
Hardware/Software Co-Design Methodology for Design of Embedded Systems. Integr. Comput. Aided Eng. 5 (1) (1998)
Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya
Transformational partitioning for co-design of multiprocessor systems. ICCAD (1997)
Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben Ismail, Ahmed Amine Jerraya
Protocol selection and interface generation for HW-SW codesign. IEEE Trans. Very Large Scale Integr. Syst. 5 (1) (1997)
Tarek Ben Ismail, Jean-Marc Daveau, Kevin O'Brien, Ahmed Amine Jerraya
A system-level communication synthesis approach for hardware/software systems. Microprocess. Microsystems 20 (3) (1996)
Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya
Synthesis of system-level communication by an allocation-based approach. ISSS (1995)