Fakhreddine Ghaffari

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 38

Top Topics

Hardware Implementation

Error Correction

Reliability Assessment

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Vivek Bansal, Otmane Aït Mohamed, Fakhreddine Ghaffari
Layout-based reliability analysis of openMSP430 register file under external radiations. ICM (2023)
Arnau Dillen, Fakhreddine Ghaffari, Olivier Romain, Bram Vanderborght, Romain Meeusen, Bart Roelands, Kevin De Pauw
Optimal Sensor Set for Decoding Motor Imagery from EEG. NER (2023)
Emmanuel Boutillon, Chris Winstead, Fakhreddine Ghaffari
The Syndrome Bit Flipping Algorithm for LDPC Codes. IEEE Commun. Lett. 27 (7) (2023)
Hangxuan Cui, Fakhreddine Ghaffari, Khoa Le, David Declercq, Jun Lin, Zhongfeng Wang
Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Fakhreddine Ghaffari, Khoa Le
An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders. ICECS (2021)
F. Cochachin, Laura Luzzi, Fakhreddine Ghaffari
Reduced Complexity of a Successive Cancellation Based Decoder for NB-Polar Codes. ISTC (2021)
Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT (2021)
Hangxuan Cui, Khoa Le, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. ISCIT (2019)
Fakhreddine Ghaffari, Khoa Le, David Declercq
The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. NEWCAS (2019)
Duc-Phuc Nguyen, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq
Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry. APCC (2019)
Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Emmanuel Boutillon, Chris Winstead, Bane Vasic
A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Duc-Phuc Nguyen, Khoa Le, Fakhreddine Ghaffari, David Declercq
Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding. ISCIT (2019)
Hangxuan Cui, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. APCC (2019)
Khoa LeTrung, Fakhreddine Ghaffari, David Declercq
An Adaptation of Min-Sum Decoder for 5G Low-Density Parity-Check Codes. ISCAS (2019)
Khoa Le, Fakhreddine Ghaffari, David Declercq
The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. MWSCAS (2018)
Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo
Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. ISCAS (2018)
David Declercq, Valentin Savin, Oana Boncalo, Fakhreddine Ghaffari
An Imprecise Stopping Criterion Based on In-Between Layers Partial Syndromes. IEEE Commun. Lett. 22 (1) (2018)
Thien Truong Nguyen-Ly, Valentin Savin, Khoa Le, David Declercq, Fakhreddine Ghaffari, Oana Boncalo
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Chris Winstead, Tasnuva Tithi, Emmanuel Boutillon, Fakhreddine Ghaffari
Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders. ISTC (2018)
Burak Unal, Ali Akoglu, Fakhreddine Ghaffari, Bane Vasic
Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2018)
Khoa Le, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin
Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Khoa Le, Fakhreddine Ghaffari, David Declercq
On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems. MWSCAS (2018)
Fakhreddine Ghaffari, Bane Vasic
Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels. ISCAS (2018)
Khoa Le, Fakhreddine Ghaffari
On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory. SSD (2018)
Yohan Baga, Morgane Richaud, Fakhreddine Ghaffari, Etienne Zante, David Declercq, Michael Nahmiyace
Probabilistic model of AFDX frames reception for end system backlog assessment. SIES (2017)
Fakhreddine Ghaffari, Burak Unal, Ali Akoglu, Khoa Le, David Declercq, Bane Vasic
Efficient FPGA implementation of probabilistic gallager B LDPC decoder. ICECS (2017)
Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin
FPGA static timing analysis enhancement based on real operating conditions. IECON (2017)
Burak Unal, Fakhreddine Ghaffari, Ali Akoglu, David Declercq, Bane Vasic
Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder. NEWCAS (2017)
Fakhreddine Ghaffari, Ali Akoglu, Bane Vasic, David Declercq
Multi-Mode Low-Latency Software-Defined Error Correction for Data Centers. ICCCN (2017)
Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin
Error rate estimation of a design implemented in an FPGA based on the operating conditions. EWDTS (2017)
Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane Vasic
Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2017)
Thien Truong Nguyen-Ly, Valentin Savin, Khoa Le, David Declercq, Fakhreddine Ghaffari, Oana Boncalo
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. CoRR (2017)
Kais Belwafi, Fakhreddine Ghaffari, Ridha Djemal, Olivier Romain
A Hardware/Software Prototype of EEG-based BCI System for Home Device Control. J. Signal Process. Syst. 89 (2) (2017)
Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane Vasic
Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. ISCAS (2017)
Kais Belwafi, Ridha Djemal, Fakhreddine Ghaffari, Olivier Romain, Bouraoui Ouni, Sofien Gannouni
Online Adaptive Filters to Classify Left and Right Hand Motor Imagery. BIOSIGNALS (2016)
Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin
Influence of high-power electric motor on an FPGA used in the drive system of electric car. IECON (2016)
Thien Truong Nguyen-Ly, Khoa Le, Valentin Savin, David Declercq, Fakhreddine Ghaffari, Oana Boncalo
Non-surjective finite alphabet iterative decoders. ICC (2016)
David Declercq, Chris Winstead, Bane V. Vasic, Fakhreddine Ghaffari, Predrag Ivanis, Emmanuel Boutillon
Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding. ISTC (2016)
Truong Nguyen-Ly, Khoa Le, Fakhreddine Ghaffari, Alexandru Amaricai, Oana Boncalo, Valentin Savin, David Declercq
FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding. NEWCAS (2015)
Andrei Hera, Oana Boncalo, Constantina-Elena Gavriliu, Alexandru Amaricai, Valentin Savin, David Declercq, Fakhreddine Ghaffari
Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders. MIXDES (2015)
Khoa Le, David Declercq, Fakhreddine Ghaffari, Christian Spagnol, Emanuel M. Popovici, Predrag Ivanis, Bane V. Vasic
Efficient realization of probabilistic gradient descent bit flipping decoders. ISCAS (2015)
Kais Belwafi, Fakhreddine Ghaffari, Olivier Romain, Ridha Djemal
An embedded implementation of home devices control system based on brain computer interface. ICM (2014)
Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado
Reliability assessment of backward error recovery for SRAM-based FPGAs. IDT (2014)
Fakhreddine Ghaffari, Fouad Sahraoui, Mohamed El Amine Benkhelifa, Bertrand Granado, Marc Alexandre Kacou, Olivier Romain
Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration. ICM (2014)
Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado
Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead. ReConFig (2014)
Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado
An efficient BER-based reliability method for SRAM-based FPGA. IDT (2013)
Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid
Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2011 (2011)
Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid
Novel Approach for Modeling Very Dynamic and Flexible Real Time Applications. ReCoSoC (2010)
Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid
Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture. IDT (2010)
Fakhreddine Ghaffari, Benoît Miramond, François Verdier
Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures. EURASIP J. Embed. Syst. 2009 (2009)
Fakhreddine Ghaffari, Benoît Miramond, François Verdier
Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip. IEEE International Workshop on Rapid System Prototyping (2008)
Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Ben Jemaa
Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures. Trans. High Perform. Embed. Archit. Compil. 1 (2007)
Fakhreddine Ghaffari, Michel Auguin
An efficient on-line Approach for on-chip HW/SW partitioner and scheduler. ARCS Workshops (2006)
Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Benjemaa
An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. DSD (2005)