Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures.
Fakhreddine GhaffariBenoît MiramondFrançois VerdierPublished in: EURASIP J. Embed. Syst. (2009)
Keyphrases
- data flow
- hw sw
- systolic array
- hardware software co design
- hardware software
- field programmable gate array
- embedded systems
- design methodology
- interconnection networks
- database machine
- control flow
- scheduling problem
- low cost
- hardware and software
- data transfer
- hardware implementation
- multi core processors
- resource constraints
- parallel algorithm
- case study
- image processing
- databases
- image processing algorithms
- high performance computing
- object oriented
- efficient implementation
- software systems
- cloud computing
- general purpose