Lounis Kessal

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 7

Top Topics

Autonomous Vehicles

Neural Architecture

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Tarek Elouaret, Sylvain Colomer, Frédéric de Melo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman
Implementation of a Bio-Inspired Neural Architecture for Autonomous Vehicles on a Multi-FPGA Platform. Sensors 23 (10) (2023)
Tarek Elouaret, Sylvain Colomer, Frederic de Melo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman
Implementation of a bio-inspired neural architecture for autonomous vehicle on a reconfigurable platform. ISIE (2022)
Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Emmanuel Boutillon, Chris Winstead, Bane Vasic
A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Tarek Elouaret, Stéphane Zuckerman, Lounis Kessal, Yoan Espada, Nicolas Cuperlier, Guillaume Bresson, Fethi Ben Ouezdou, Olivier Romain
Position Paper: Prototyping Autonomous Vehicles Applications with Heterogeneous Multi-FpgaSystems. UCET (2019)
Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo
Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. ISCAS (2018)
Khoa Le, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin
Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Franklin Cochachin, David Declercq, Emmanuel Boutillon, Lounis Kessal
Density evolution thresholds for noise-against-noise min-sum decoders. PIMRC (2017)
Lotfi Bendaouia, Hassen Salhi, Si Mahmoud Karabernou, Lounis Kessal, Fayçal Ykhlef
FPGA-implementation of a bio-inspired medical hearing aid based DWT-OLA. ICAILP (2014)
Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Lounis Kessal, Fabrice Lemonnier, Jimmy Le Rhun
Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications. ACM Trans. Reconfigurable Technol. Syst. 5 (3) (2012)
Laurent Gantel, Amel Khiar, Benoît Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal
Dataflow programming model for reconfigurable computing. ReCoSoC (2011)
Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal
Hardware Architecture for Pattern Recognition in Gamma-Ray Experiment. EURASIP J. Embed. Syst. 2009 (2009)
Lounis Kessal, Nicolas Abel, Si Mahmoud Karabernou, Didier Demigny
Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing. J. Real Time Image Process. 3 (3) (2008)
Narayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal
Neural network hardware architecture for pattern recognition in the HESS2 project. ESANN (2008)
Si Mahmoud Karabernou, Lounis Kessal, Fayçal Terranti
Erratum to "Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm" [Image and Vision Computing 23 (2005) 1009-1017]. Image Vis. Comput. 25 (6) (2007)
Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny
Clear Stream towards Dynamically Reconfigurable Systems on Chip. ReCoSoC (2006)
Nicolas Abel, Lounis Kessal, Didier Demigny
Design flexibility using fpga dynamical reconfiguration. ICIP (2004)
Lounis Kessal, Nicolas Abel, Didier Demigny
Real-time image processing with dynamically reconfigurable architecture. Real Time Imaging 9 (5) (2003)
Didier Demigny, Lounis Kessal, J. Pons
Fast Recursive Implementation of the Gaussian Filter. VLSI-SOC (2001)
P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, Si Mahmoud Karabernou
Two ASIC for Low and Middle Levels of Real Time Image Processing. VLSI-SOC (2001)
Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, Si Mahmoud Karabernou
Reconfigurable Architecture Using High Speed FPGA. VLSI-SOC (2001)
Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani
How to Use High Speed Reconfigurable FPGA for Real Time Image Processing? CAMP (2000)
Lounis Kessal, Didier Demigny, N. Boudouani, R. Bourguiba
Reconfigurable Hardware for Real Time Image Processing. ICIP (2000)
F. G. Lorca, Lounis Kessal, Didier Demigny
Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. ICIP (2) (1997)
Didier Demigny, F. G. Lorca, Lounis Kessal
Evaluation of edge detectors performances with a discrete expression of Canny's criteria. ICIP (1995)