Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes.
Khoa LeFakhreddine GhaffariLounis KessalDavid DeclercqValentin SavinOana BoncaloPublished in: ISCAS (2018)
Keyphrases
- lightweight
- hardware architecture
- ldpc codes
- decoding algorithm
- hardware implementation
- error correction
- message passing
- xilinx virtex
- block cipher
- low density parity check
- associative memory
- bayesian networks
- probabilistic model
- noise model
- non binary
- wireless sensor networks
- neural network
- field programmable gate array
- belief propagation
- image transmission
- pairwise