Sébastien Pillement

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 24

Top Topics

Error Detection

Formal Verification

Cooperative Spectrum Sensing

Energy Efficient

Top Venues

Publications

Juliette Pottier, Thomas Nieddu, Bertrand Le Gal, Sébastien Pillement, Maria Méndez Real
RISC-V processor enhanced with a dynamic micro-decoder unit. CoRR (2024)
Quentin Dariol, Sébastien Le Nours, Domenik Helms, Ralf Stemmer, Sébastien Pillement, Kim Grüttner
Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms. DroneSE/RAPIDO@HiPEAC (2023)
Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, B. Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, A. Sintzoff, J. R. Coulon
Securing a RISC-V architecture: A dynamic approach. DATE (2023)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
Formal Verification of Divider Circuits by Hardware Reduction. SMACD (2023)
Alexis Duhamel, Sébastien Pillement
QoS Aware Design-Time/Run-Time Manager for FPGA-Based Embedded Systems. DASIP (2022)
Quentin Dariol, Sebastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms, Kim Grüttner
A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms. SAMOS (2022)
Hai-Dang Vu, Sebastien Le Nours, Sébastien Pillement, Ralf Stemmer, Kim Grüttner
A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC. ASP-DAC (2021)
Simei Yang, Sebastien Le Nours, Maria Mendez Real, Sébastien Pillement
0-1 ILP-based run-time hierarchical energy optimization for heterogeneous cluster-based multi/many-core systems. J. Syst. Archit. 116 (2021)
Hai-Dang Vu, Sebastien Le Nours, Sébastien Pillement
Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems. DSD (2021)
Safouane Noubir, Maria Mendez Real, Sébastien Pillement
Towards Malicious Exploitation of Energy Management Mechanisms. DATE (2020)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. DATE (2020)
Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. ISVLSI (2020)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
Functional Verification of Hardware Dividers using Algebraic Model. VLSI-SoC (2019)
Ralf Stemmer, Hai-Dang Vu, Kim Grüttner, Sebastien Le Nours, Wolfgang Nebel, Sébastien Pillement
Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs. SAMOS (2019)
Simei Yang, Sebastien Le Nours, Maria Mendez Real, Sébastien Pillement
System-Level Modeling and Simulation of MPSoC Run-Time Management Using Execution Traces Analysis. SAMOS (2019)
Simei Yang, Sebastien Le Nours, Maria Mendez Real, Sébastien Pillement
Mapping and Frequency Joint Optimization for Energy Efficient Execution of Multiple Applications on Multicore Systems. DASIP (2019)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
Formal Verification of Integer Dividers: Division by a Constant. ISVLSI (2019)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. EDCC (2018)
Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel E. Holcomb, Russell Tessier
FPGA Side Channel Attacks without Physical Access. FCCM (2018)
Tien Thanh Nguyen, Mathieu Thevenin, Anthony Mouraud, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement
High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques. IPDPS Workshops (2018)
Shaoyang Men, Pascal Chargé, Sébastien Pillement
Cooperative Spectrum Sensing with Small Sample Size in Cognitive Wireless Sensor Networks. Wirel. Pers. Commun. 96 (2) (2017)
Tien Thanh Nguyen, Anthony Mouraud, Mathieu Thevenin, Gwenolé Corre, Olivier Pasquier, Sébastien Pillement
Model-driven reliability evaluation for MPSoC design. DASIP (2017)
Wei He, Sébastien Pillement, Du Xu
FTUC: A Flooding Tree Uneven Clustering Protocol for a Wireless Sensor Network. Sensors 17 (12) (2017)
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
Hardware runtime verification of embedded software in SoPC. SIES (2016)
B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak
Fault-aware configurable logic block for reliable reconfigurable FPGAs. ISCAS (2015)
Shaoyang Men, Pascal Chargé, Sébastien Pillement
A Robust and Energy Efficient Cooperative Spectrum Sensing Scheme in Cognitive Wireless Sensor Networks. Netw. Protoc. Algorithms 7 (3) (2015)
Shaoyang Men, Pascal Chargé, Sébastien Pillement
A robust cooperative spectrum sensing method against faulty nodes in CWSNs. ICC Workshops (2015)
Romain Brillu, Sébastien Pillement, Fabrice Lemonnier, Philippe Millet, Eric Lenormand, Marc Bernot, Frédéric Falzon
Towards a Design Space Exploration Tool for MPSoC Platforms Designs: A Case Study. PDP (2014)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38 (2) (2014)
Romain Brillu, Sébastien Pillement, Aymen Abdellah, Fabrice Lemonnier, Philippe Millet
FlexTiles: a globally homogeneous but locally heterogeneous manycore architecture. RAPIDO (2014)
Ludovic Devaux, Sébastien Pillement
OCEAN, a flexible adaptive Network-On-Chip for dynamic applications. Microprocess. Microsystems 38 (4) (2014)
B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. ARC (2014)
Loïc Lagadec, Sébastien Pillement, Arnaud Tisserand
Introduction. Tech. Sci. Informatiques 32 (2) (2013)
Quang-Hai Khuat, Quang-Hoa Le, Daniel Chillet, Sébastien Pillement
Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture. IDT (2013)
Hung-Manh Pham, Sébastien Pillement, Stanislaw J. Piestrak
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor. IEEE Trans. Computers 62 (6) (2013)
Romain Brillu, Sébastien Pillement, Fabrice Lemonnier, Philippe Millet
Cluster based MPSoC architecture: an on-chip message passing implementation. Des. Autom. Embed. Syst. 17 (3-4) (2013)
Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet
UPaRC - Ultra-fast power-aware reconfiguration controller. DATE (2012)
Istas Pratomo, Sébastien Pillement
Gradient - An adaptive fault-tolerant routing algorithm for 2D mesh Network-on-Chips. DASIP (2012)
Istas Pratomo, Sébastien Pillement
Impact of design parameters on performance of adaptive Network-on-Chips. HPCS (2012)
Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. ICSAMOS (2012)
Hung-Manh Pham, Ludovic Devaux, Sébastien Pillement
DA: Reliable and reconfigurable dynamic architecture. ReCoSoC (2011)
Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. VLSI-SoC (2011)
Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis
Hardware OS Communication Service and Dynamic Memory Management for RSoCs. ReConFig (2011)
Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Parallel Evaluation of Hopfield Neural Networks. IJCCI (NCTA) (2011)
Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. J. Syst. Archit. 57 (4) (2011)
Hung-Manh Pham, Sébastien Pillement, Olivier Pasquier, Sebastien Le Nours
A framework for the design of reconfigurable fault tolerant architectures. DASIP (2011)
Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
Error recovery technique for coarse-grained reconfigurable architectures. DDECS (2011)
Hung-Manh Pham, Sébastien Pillement, Didier Demigny
Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC. FPL (2010)
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". IEEE Commun. Lett. 14 (8) (2010)
Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. ReConFig (2010)
Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2010 (2010)
Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Task placement for dynamic and partial reconfigurable architecture. DASIP (2010)
Sébastien Pillement, Olivier Sentieys, Jean-Marc Philippe
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect. Microelectron. J. 41 (8) (2010)
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. IEEE Trans. Circuits Syst. II Express Briefs (10) (2010)
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
Design of a fault-tolerant coarse-grained. ISQED (2010)
Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny
Mesh and Fat-Tree comparison for dynamically reconfigurable applications. ReCoSoC (2010)
Hung-Manh Pham, Sébastien Pillement, Didier Demigny
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip. ReConFig (2009)
Julien Lallet, Sébastien Pillement, Olivier Sentieys
xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. DSD (2009)
Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet
High-Level Exploration for Dynamic Reconfiguration Management. ERSA (2009)
Benoît Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, Thomas LeFebvre, Mehdi Aïchouch, Jean-Christophe Prévotet, Yaset Oliva, Daniel Chillet, Sébastien Pillement
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. Int. J. Reconfigurable Comput. 2009 (2009)
Julien Lallet, Sébastien Pillement, Olivier Sentieys
Efficient dynamic reconfiguration for multi-context embedded FPGA. SBCCI (2008)
Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig (2008)
Sébastien Pillement, Olivier Sentieys, Raphaël David
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency. EURASIP J. Embed. Syst. 2008 (2008)
Sébastien Pillement, Raphaël David
Architectures reconfigurable et faible consommation. Réalité ou prospective ? Tech. Sci. Informatiques 26 (5) (2007)
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS (2007)
Imene Benkermi, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Hardware task scheduling for heterogeneous soc architectures. EUSIPCO (2007)
Daniel Chillet, Sébastien Pillement, Olivier Sentieys
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN (2007)
Jean-Marc Philippe, E. Kinvi-Boh, Sébastien Pillement, Olivier Sentieys
An energy-efficient ternary interconnection link for asynchronous systems. ISCAS (2006)
Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. ISQED (2006)
Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny
Clear Stream towards Dynamically Reconfigurable Systems on Chip. ReCoSoC (2006)
Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys
A low-power and high-speed quaternary interconnection link using efficient converters. ISCAS (5) (2005)
Raphaël David, Dominique Lavenier, Sébastien Pillement
Du microprocesseur au circuit FPGA. Une analyse sous l'angle de la reconfiguration. Tech. Sci. Informatiques 24 (4) (2005)
François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC (2005)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture. ICASSP (2002)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS (2002)
Sébastien Pillement, Daniel Chillet, Olivier Sentieys
Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED (2002)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL (2002)
Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC (2001)
Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
Fast Prototyping: A Case Study - The JPEG Compression Algorithm. IEEE International Workshop on Rapid System Prototyping (1999)
S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. VLSI (1999)
Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon
Concurrent Design of Hardware/Software Dedicated Systems. FPL (1996)