Formal Verification of Divider Circuits by Hardware Reduction.
Atif YasinTiankai SuSébastien PillementMaciej J. CiesielskiPublished in: SMACD (2023)
Keyphrases
- formal verification
- model checking
- clock gating
- circuit design
- digital circuits
- power reduction
- model checker
- symbolic model checking
- real time
- automated verification
- low cost
- bounded model checking
- hardware and software
- hardware implementation
- high speed
- floating gate
- temporal logic
- computer systems
- low power
- program slicing
- power consumption
- analog circuits
- open source
- delay insensitive
- logic synthesis
- chip design
- field programmable gate array
- formal specification
- functional verification
- model based diagnosis