Maciej J. Ciesielski

ORCID

Publication Activity (10 Years)

Years Active: 1981-2024
Publications (10 Years): 33

Top Venues

ISVLSI

CoRR

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

DATE

Publications

Jiteshri Dasari, Maciej J. Ciesielski
Combining Formal Verification and Testing for Debugging of Arithmetic Circuits. DATE (2024)
Jiteshri Dasari, Maciej J. Ciesielski
Efficient Formal Verification and Debugging of Arithmetic Divider Circuits. ICCAD (2023)
Maciej J. Ciesielski
Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future. DSD (2023)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
Formal Verification of Divider Circuits by Hardware Reduction. SMACD (2023)
Jiteshri Dasari, Maciej J. Ciesielski
Formal Verification of Restoring Dividers made Fast and Simple. DAC (2023)
Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari
Functional Verification of Arithmetic Circuits: Survey of Formal Methods. DDECS (2022)
Maciej J. Ciesielski, Tiankai Su, Atif Yasin, Cunxi Yu
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (6) (2020)
Dinesh D. Narasimharaju, R. S. Suraj Rao, Akshaya Sandeep Waingade, Atif Yasin, Maciej J. Ciesielski
Dual Approach to Solving SAT in Hardware. DTIS (2020)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. DATE (2020)
Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. ISVLSI (2020)
Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski
Spectral approach to verifying non-linear arithmetic circuits. ASP-DAC (2019)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
Functional Verification of Hardware Dividers using Algebraic Model. VLSI-SoC (2019)
Cunxi Yu, Maciej J. Ciesielski
Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (2) (2019)
Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski
Spectral Approach to Verifying Non-linear Arithmetic Circuits. CoRR (2019)
Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski
Formal Verification of Integer Dividers: Division by a Constant. ISVLSI (2019)
Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski
Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. ISCAS (2018)
Cunxi Yu, Maciej J. Ciesielski, Alan Mishchenko
Fast Algebraic Rewriting Based on And-Inverter Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (9) (2018)
Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli
End-to-End Industrial Study of Retiming. ISVLSI (2018)
Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski
Rewriting Environment for Arithmetic Circuit Verification. LPAR (2018)
Cunxi Yu, Maciej J. Ciesielski
Formal Analysis of Galois Field Arithmetics - Parallel Verification and Reverse Engineering. CoRR (2018)
Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski
Advanced datapath synthesis using graph isomorphism. ICCAD (2017)
Cunxi Yu, Maciej J. Ciesielski
Efficient parallel verification of Galois field multipliers. ASP-DAC (2017)
Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski
Advanced Datapath Synthesis using Graph Isomorphism. CoRR (2017)
Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski
) arithmetic. DATE (2017)
Cunxi Yu, Xiangyu Zhang, Duo Liu, Maciej J. Ciesielski, Daniel E. Holcomb
Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (10) (2017)
Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. ISVLSI (2017)
Cunxi Yu, Maciej J. Ciesielski
Efficient Parallel Verification of Galois Field Multipliers. CoRR (2016)
Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski
Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic. CoRR (2016)
Cunxi Yu, Maciej J. Ciesielski
Automatic word-level abstraction of datapath. ISCAS (2016)
Cunxi Yu, Maciej J. Ciesielski
Formal Verification Using Don't-Care and Vanishing Polynomials. ISVLSI (2016)
Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan
DAG-aware logic synthesis of datapaths. DAC (2016)
Cunxi Yu, Walter Brown, Duo Liu, André Rossi, Maciej J. Ciesielski
Formal Verification of Arithmetic Circuits by Function Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (12) (2016)
Cunxi Yu, Maciej J. Ciesielski
Analyzing Imprecise Adders Using BDDs - A Case Study. ISVLSI (2016)
Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi
Verification of gate-level arithmetic circuits by function extraction. DAC (2015)
Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski
Logic Debugging of Arithmetic Circuits. ISVLSI (2015)
Cunxi Yu, Walter Brown, Maciej J. Ciesielski
Verification of arithmetic datapath designs using word-level approach - A case study. ISCAS (2015)
Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli
Exploiting Circuit Duality to Speed up SAT. ISVLSI (2015)
Tariq B. Ahmad, Maciej J. Ciesielski
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. ISVLSI (2014)
Tariq Bashir Ahmad, Maciej J. Ciesielski
Fast time-parallel C-based event-driven RTL simulation. DDECS (2014)
Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi
Function Extraction from Arithmetic Bit-Level Circuits. ISVLSI (2014)
Tariq B. Ahmad, Maciej J. Ciesielski
Fast STA prediction-based gate-level timing simulation. DATE (2014)
Maciej J. Ciesielski, Walter Brown, André Rossi
Arithmetic Bit-Level Verification Using Network Flow Model. Haifa Verification Conference (2013)
Tariq Bashir Ahmad, Maciej J. Ciesielski
An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads. MTV (2013)
Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier
FPGA latency optimization using system-level transformations and DFG restructuring. DATE (2013)
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE (2011)
Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design (2011)
Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
A new distributed event-driven gate-level HDL simulation by accurate prediction. DATE (2011)
Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej J. Ciesielski
Algebraic approach to arithmetic design verification. FMCAD (2011)
Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electron. 7 (4) (2011)
Maciej J. Ciesielski, Anna Kaminska
and their applications. J. Approx. Theory 162 (9) (2010)
Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. HLDVT (2010)
Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon
High-Level Dataflow Transformations Using Taylor Expansion Diagrams. IEEE Des. Test Comput. 26 (4) (2009)
Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon
Optimizing data flow graphs to minimize hardware implementation. DATE (2009)
Maciej J. Ciesielski, Daniel Gomez-Prado, Qian Ren, Jérémie Guillot, Emmanuel Boutillon
Optimization of Data-Flow Computations Using Canonical TED Representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (9) (2009)
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
Temporal parallel gate-level timing simulation. HLDVT (2008)
Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang
A fast two-pass HDL simulation with on-demand dump. ASP-DAC (2008)
Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang
Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design (2008)
Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon
Data-flow transformations using Taylor expansion diagrams. DATE (2007)
Jérémie Guillot, Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar
Efficient factorization of DSP transforms using taylor expansion diagrams. DATE (2006)
Maciej J. Ciesielski, Priyank Kalla, Serkan Askar
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers 55 (9) (2006)
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
Yield-aware Floorplanning. DSD (2005)
Fei Xin, Maciej J. Ciesielski, Ian G. Harris
Design validation of behavioral VHDL descriptions for arbitrary fault models. ETS (2005)
Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski
Functional test generation based on word-level SAT. J. Syst. Archit. 51 (8) (2005)
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
An ILP Formulation for Yield-driven Architectural Synthesis. DFT (2005)
Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski
Algorithms for Taylor Expansion Diagrams. ISMVL (2004)
Daniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon
Variable ordering for taylor expansion diagrams. HLDVT (2004)
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski
A new state assignment technique for testing and low power. DAC (2004)
Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski
Mathematical framework for representing discrete functions as word-level polynomials. HLDVT (2003)
Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski
Fast Computation of Data Correlation Using BDDs. DATE (2003)
Priyank Kalla, Maciej J. Ciesielski
A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (7) (2002)
Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE (2002)
Maciej J. Ciesielski, Serkan Askar, Samuel Levitin
Analytical approach to layout generation of datapath cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (12) (2002)
Congguang Yang, Maciej J. Ciesielski
BDS: a BDD-based logic optimization system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (7) (2002)
Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin
High-level design verification using Taylor Expansion Diagrams: first results. HLDVT (2002)
Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski
LPSAT: a unified approach to RTL satisfiability. DATE (2001)
Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre
Taylor expansion diagrams: a new representation for RTL verification. HLDVT (2001)
Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski
Strategies for solving the Boolean satisfiability problem using binary decision diagrams. J. Syst. Archit. 47 (6) (2001)
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
Functional Test Generation using Constraint Logic Programming. VLSI-SOC (2001)
Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
BDS: a BDD-based logic optimization system. DAC (2000)
Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE (2000)
Congguang Yang, Maciej J. Ciesielski
Synthesis for Mixed CMOS/PTl Logic. DATE (2000)
Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski
Retiming-based factorization for sequential logic optimization. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Priyank Kalla, Maciej J. Ciesielski
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE (1999)
Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
BDD Decomposition for Efficient Logic Synthesis. ICCD (1999)
Durgam Vahia, Maciej J. Ciesielski
Transistor level placement for full custom datapath cell design. ISPD (1999)
Serkan Askar, Maciej J. Ciesielski
Analytical approach to custom datapath design. ICCAD (1999)
Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu
Wave-pipelining: a tutorial and research survey. IEEE Trans. Very Large Scale Integr. Syst. 6 (3) (1998)
Balakrishnan Iyer, Maciej J. Ciesielski
Reencoding for cycle-time minimization under fixed encoding length. ICCAD (1998)
Priyank Kalla, Maciej J. Ciesielski
A comprehensive approach to the partial scan problem using implicit state enumeration. ITC (1998)
Priyank Kalla, Maciej J. Ciesielski
Testability of Sequential Circuits with Multi-Cycle False Path. VTS (1997)
Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga
Intelligent Simulation for Computer Aided Design of Optical Networks. ONDM (1997)
Balakrishnan Iyer, Maciej J. Ciesielski
Metamorphosis: state assignment by retiming and re-encoding. ICCAD (1996)
Zafar Hasan, Maciej J. Ciesielski
FSM Decomposition and Functional Verification of FSM Networks. VLSI Design 3 (3-4) (1995)
Zafar Hasan, Maciej J. Ciesielski
Elimination of multi-cycle false paths by state encoding. ED&TC (1995)
Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski
Forum: Wave-pipelining: Is it Practical? ISCAS (1994)
Zafar Hasan, Maciej J. Ciesielski
Functional verification and simulation of FSM networks. VTS (1993)
Donald A. Joy, Maciej J. Ciesielski
Clock period minimization with wave pipelining. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (4) (1993)
Zafar Hasan, David Harrison, Maciej J. Ciesielski
A Fast Partitioning Method for PLA-Based FPGAs. IEEE Des. Test Comput. 9 (4) (1992)
Maya K. Yajnik, Maciej J. Ciesielski
Finite State Machine Decomposition Using Multiway Partitioning. ICCD (1992)

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Publication Activity (10 Years)

Top Topics

Top Venues

Maciej J. Ciesielski