Verification of gate-level arithmetic circuits by function extraction.

Maciej J. Ciesielski Cunxi Yu Walter Brown Duo Liu André Rossi

Published in: DAC (2015)

Keyphrases

asynchronous circuits
image segmentation
high speed
automatic extraction
neural network
information extraction
model checking
cmos technology
machine learning
website
low cost
temporal logic
transfer function
levels of abstraction
floating point
multiple input