Walter Brown

Publication Activity (10 Years)

Years Active: 2008-2016
Publications (10 Years): 1

Top Topics

Formal Verification

Top Venues

Haifa Verification Conference

Publications

Cunxi Yu, Walter Brown, Duo Liu, André Rossi, Maciej J. Ciesielski
Formal Verification of Arithmetic Circuits by Function Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (12) (2016)
Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi
Verification of gate-level arithmetic circuits by function extraction. DAC (2015)
Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski
Logic Debugging of Arithmetic Circuits. ISVLSI (2015)
Cunxi Yu, Walter Brown, Maciej J. Ciesielski
Verification of arithmetic datapath designs using word-level approach - A case study. ISCAS (2015)
Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi
Function Extraction from Arithmetic Bit-Level Circuits. ISVLSI (2014)
Maciej J. Ciesielski, Walter Brown, André Rossi
Arithmetic Bit-Level Verification Using Network Flow Model. Haifa Verification Conference (2013)
Walter Brown
Innovations for digital inclusion: Leveraging next generation networks for human development from the bottom of the pyramid. Kaleidoscope (2009)
Walter Brown, Irwin Brown
Towards a research framework for a human development-based "bottom of the pyramid" ICT development strategy in South Africa. ECIS (2009)
Walter Brown, Irwin Brown
Next generation ICT policy in South Africa: Towards a human development-based ICT policy. HCC (2008)