Dusung Kim

Publication Activity (10 Years)

Years Active: 2008-2013
Publications (10 Years): 0

Top Topics

Simulation Model

Information Delivery

Asynchronous Cellular Automata

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE (2011)
Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
A new distributed event-driven gate-level HDL simulation by accurate prediction. DATE (2011)
Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. HLDVT (2010)
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
Temporal parallel gate-level timing simulation. HLDVT (2008)
Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang
A fast two-pass HDL simulation with on-demand dump. ASP-DAC (2008)