Seiyang Yang

Publication Activity (10 Years)

Years Active: 1989-2014
Publications (10 Years): 0

Top Topics

Information Delivery

Asynchronous Cellular Automata

Simulation Models

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy. DATE (2014)
Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. DATE (2011)
Dusung Kim, Maciej J. Ciesielski, Seiyang Yang
A new distributed event-driven gate-level HDL simulation by accurate prediction. DATE (2011)
Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang
Temporal parallel gate-level timing simulation. HLDVT (2008)
Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang
A fast two-pass HDL simulation with on-demand dump. ASP-DAC (2008)
Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang
Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design (2008)
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski
A new state assignment technique for testing and low power. DAC (2004)
Maciej J. Ciesielski, Seiyang Yang
PLADE: a two-stage PLA decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (8) (1992)
Seiyang Yang, Maciej J. Ciesielski
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (1) (1991)
Seiyang Yang, Maciej J. Ciesielski
PLA decomposition with generalized decoders. ICCAD (1989)