Kesava R. Talupuru

Publication Activity (10 Years)

Years Active: 2005-2011
Publications (10 Years): 0

Publications

Kesava R. Talupuru, Sanjai Athi
Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking. MTV (2011)
Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang
Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design (2008)
Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski
Functional test generation based on word-level SAT. J. Syst. Archit. 51 (8) (2005)