Sign in
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
Shibaji Banerjee
Jimson Mathew
Saraju P. Mohanty
Dhiraj K. Pradhan
Maciej J. Ciesielski
Published in:
J. Low Power Electron. (2011)
Keyphrases
</>
real time
global optimization
power consumption
data sets
high speed
optimization algorithm
constrained optimization
low cost
optimization method
optimization methods
optimization process
knowledge transfer
levels of abstraction
learning algorithm
nano scale