Eric Martin

Publication Activity (10 Years)

Years Active: 1993-2021
Publications (10 Years): 1

Top Topics

Conceptual Framework

Manufacturing Processes

Top Venues

Publications

Nathalie Julien, Eric Martin
Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology. SOHOMA (2021)
Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin
A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI (2012)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS (2011)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP (2011)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS (2010)
Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures CoRR (2010)
Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL (2010)
Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin
Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS (2010)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP (2010)
Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. J. Signal Process. Syst. 56 (2-3) (2009)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
Estimation et optimisation de la consommation des mémoires. Tech. Sci. Informatiques 27 (1-2) (2008)
Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. EUSIPCO (2007)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
Constrained algorithmic IP design for system-on-chip. Integr. 40 (2) (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Application of a design space exploration tool to enhance interleaver generation CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Design Methodology for Space-Time Adapter CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Application of a design space exploration tool to enhance interleaver generation. EUSIPCO (2007)
Pierre Bomel, Eric Martin, Emmanuel Boutillon
Synchronization Processor Synthesis for Latency Insensitive Systems CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels CoRR (2007)
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD (2007)
Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power CoRR (2006)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
Memory Aware High-Level Synthesis for Embedded Systems CoRR (2006)
Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
A Memory Aware High Level Synthesis Too CoRR (2006)
Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin
G729 Voice Decoder Design. J. VLSI Signal Process. 42 (2) (2006)
Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
High-level synthesis under I/O Timing and Memory constraints CoRR (2006)
Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS (2006)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5 (1) (2006)
Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI CoRR (2006)
Guillaume Savaton, Emmanuel Casseau, Eric Martin
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. Signal Process. 86 (7) (2006)
Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) (2005)
Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin
C-based rapid prototyping for digital signal processing. EUSIPCO (2005)
Bertrand Le Gal, Emmanuel Casseau, Eric Martin
Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. EUSIPCO (2005)
Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
High-level synthesis under I/O timing and memory constraints. ISCAS (1) (2005)
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI (2005)
Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart
SystemCmantic: A high level Modelling and Co-Design Framework. FDL (2005)
Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
High-Level Synthesis in Latency Insensitive System Methodology. DSD (2005)
Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. SAMOS (2005)
Pierre Bomel, Eric Martin, Emmanuel Boutillon
Synchronization Processor Synthesis for Latency Insensitive Systems. DATE (2005)
Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications. EURASIP J. Adv. Signal Process. 2005 (16) (2005)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI (2004)
David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. DSD (2004)
Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
Memory accesses management during high level synthesis. CODES+ISSS (2004)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
Memory Aware HLS and the Implementation of Ageing Vectors. DSD (2004)
David Gnaedig, Emmanuel Boutillon, Eric Martin, Amor Nafkha, Michel Jézéquel, Jacky Tousch, Nathalie Brengarth
Synthèse d'architecture pour la réalisation comportementale de l'algorithme MAP pour Turbo Décodeur. Ann. des Télécommunications 59 (3-4) (2004)
Emmanuel Casseau, Christophe Jégo, Eric Martin
Synthèse architecturale d'applications temps réel pour technologies submicroniques. Tech. Sci. Informatiques 23 (1) (2004)
Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin
A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. ICASSP (5) (2004)
Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin
Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) (2004)
Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. DATE (2004)
Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. PATMOS (2004)
Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin
A Complete Methodology for Memory Optimization in DSP Applications. DSD (2004)
Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
A Memory Aware High Level Synthesis Tool . ISVLSI (2004)
Nathalie Julien, S. Gailhard, Eric Martin
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT. J. VLSI Signal Process. 35 (2) (2003)
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. DATE (2003)
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Eric Martin
A simulation based approach for incorporating virtual components IP cores into multimedia systems design. ICME (2003)
Philippe Coussy, Adel Baganne, Eric Martin
Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC (2003)
Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
Power Consumption Modeling and Characterization of the TI C6201. IEEE Micro 23 (5) (2003)
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Eric Martin
A simulation based approach for incorporating virtual components IP cores into multimedia systems design. ICASSP (2) (2003)
Philippe Coussy, Adel Baganne, Eric Martin
A design methodology for integrating IP into SOC systems. CICC (2002)
Philippe Coussy, Adel Baganne, Eric Martin
Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. ICECS (2002)
Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. ISHPC (2002)
Philippe Coussy, Adel Baganne, Eric Martin
IP cores integration in DSP System-on-chip designs. EUSIPCO (2002)
Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin
Power Consumption Estimation of a C Program for Data-Intensive Applications. PATMOS (2002)
Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin
High-level design verification using Taylor Expansion Diagrams: first results. HLDVT (2002)
Philippe Coussy, Adel Baganne, Eric Martin
A design methodology for IP integration. ISCAS (4) (2002)
Eric Senn, Eric Martin
A Vision System on Chip for Industrial Control. VLSI-SOC (2001)
Emmanuel Casseau, Christophe Jégo, Eric Martin
Architectural synthesis of digital signal processing applications dedicated to submicron technologies. ICECS (2001)
Eric Senn, D. Emzivat, Eric Martin
A smart "single line" pixel sensor for industrial vision. ICECS (2001)
Adel Baganne, Jean Luc Philippe, Eric Martin
A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller. J. VLSI Signal Process. 22 (1) (1999)
Christophe Jégo, Emmanuel Casseau, Eric Martin
Architectural Synthesis with Interconnection Cost Control. VLSI (1999)
S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. Great Lakes Symposium on VLSI (1999)
Stephane Gailhard, Nathalie Julien, Eric Martin
Adaptive filters implementation performances under power dissipation constraint. EUSIPCO (1998)
S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. Great Lakes Symposium on VLSI (1998)
Adel Baganne, Jean Luc Philippe, Eric Martin
Hardware interface design for real time embedded systems. Great Lakes Symposium on VLSI (1997)
Eric Martin, Olivier Sentieys, Hélène Dubois, Jean Luc Philippe
GAUT: An architectural synthesis tool for dedicated signal processors. EURO-DAC (1993)