Pierre Bomel

Publication Activity (10 Years)

Years Active: 2004-2018
Publications (10 Years): 7

Top Topics

Deadlock Detection

Routing Algorithm

Top Venues

Publications

Asma Benmessaoud Gabis, Pierre Bomel, Marc Sevaux
Bi-Objective Cost Function for Adaptive Routing in Network-on-Chip. IEEE Trans. Multi Scale Comput. Syst. 4 (2) (2018)
Asma Benmessaoud Gabis, Pierre Bomel, Marc Sevaux
Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip. Microprocess. Microsystems 61 (2018)
Erwan Moreac, André Rossi, Johann Laurent, Pierre Bomel
Bit-accurate energy estimation for Networks-on-Chip. J. Syst. Archit. 77 (2017)
Erwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi
Energy aware Networks-on-Chip cortex inspired communication. PATMOS (2017)
Erwan Moreac, Pierre Bomel, Johann Laurent, André Rossi
Energy Savings in Networks-on-Chip with Smart Temporal Shielding. J. Low Power Electron. 13 (3) (2017)
Erwan Moreac, André Rossi, Johann Laurent, Pierre Bomel
Crosstalk-aware link power model for Networks-on-Chip. DASIP (2016)
Asma Benmessaoud Gabis, Marc Sevaux, Pierre Bomel, Mouloud Koudil, Karima Benatchba
Heuristic Based Routing Algorithm for Network on Chip. MCSoC (2016)
Yaset Oliva, Emmanuel Casseau, Kevin J. M. Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin, Laurent Morin
Orcc's compa-backend demonstration. DASIP (2014)
Pierre Bomel, Kevin J. M. Martin, Jean-Philippe Diguet
Virtual Devices for Hot-Pluggable Processors. DSD (2014)
Pierre Bomel, Kevin J. M. Martin, Jean-Philippe Diguet
Virtual UARTs for Reconfigurable Multi-processor Architectures. IPDPS Workshops (2013)
Pierre Bomel, Marc Sevaux
Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations. DSD (2013)
Pierre Bomel, Dominique Blouin, Mickael Lanoe, Eric Senn
Functional validation of AADL models via model transformation to SystemC with ATL. ACES-MB@MoDELS (2012)
Guy Gogniat, Jorgiano Vidal, Linfeng Ye, Jérémie Crenne, Sébastien Guillet, Florent de Lamotte, Jean-Philippe Diguet, Pierre Bomel
Self-reconfigurable Embedded Systems: From Modeling to Implementation. ERSA (2010)
Emmanuel Boutillon, Yangyang Tang, Cédric Marchand, Pierre Bomel
Hardware Discrete Channel Emulator. HPCS (2010)
Pierre Bomel, Jérémie Crenne, Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat
Ultra-Fast Downloading of Partial Bitstreams through Ethernet. ARCS (2009)
Jean-Philippe Diguet, Linfeng Ye, Yvan Eustache, Jérémie Crenne, Pierre Bomel, Guy Gogniat, Jorgiano Vidal, Florent de Lamotte
Networked Self-adaptive Systems: An Opportunity for Configuring in the Large. ERSA (2009)
Pierre Bomel, Guy Gogniat, Jean-Philippe Diguet
A Networked, Lightweight and Partially Reconfigurable Platform. ARC (2008)
Rasmus Abildgren, Jean-Philippe Diguet, Pierre Bomel, Guy Gogniat, Peter Koch, Yannick Le Moullec
A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis. EURASIP J. Embed. Syst. 2008 (2008)
Pierre Bomel, Jean-Philippe Diguet, Guy Gogniat, Jérémie Crenne
Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. ISPDC (2008)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
Constrained algorithmic IP design for system-on-chip. Integr. 40 (2) (2007)
Pierre Bomel, Eric Martin, Emmanuel Boutillon
Synchronization Processor Synthesis for Latency Insensitive Systems CoRR (2007)
Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
High-level synthesis under I/O Timing and Memory constraints CoRR (2006)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5 (1) (2006)
Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI CoRR (2006)
Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) (2005)
Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin
C-based rapid prototyping for digital signal processing. EUSIPCO (2005)
Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
High-level synthesis under I/O timing and memory constraints. ISCAS (1) (2005)
Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno
Hardware Virtual Components Compliant with Communication System Standards. DSD (2005)
Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
High-Level Synthesis in Latency Insensitive System Methodology. DSD (2005)
Pierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. SAMOS (2005)
Pierre Bomel, Eric Martin, Emmanuel Boutillon
Synchronization Processor Synthesis for Latency Insensitive Systems. DATE (2005)
Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
Memory accesses management during high level synthesis. CODES+ISSS (2004)