Philippe Coussy

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 27

Top Topics

Automatically Generate

Energy Efficient

Hardware Architectures

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
CREPE: Concurrent Reverse-Modulo-Scheduling and Placement for CGRAs. IEEE Trans. Parallel Distributed Syst. 35 (7) (2024)
Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications. DASIP (2024)
Satyajit Das, Kevin J. M. Martin, Thomas Peyret, Philippe Coussy
An Efficient and Flexible Stochastic CGRA Mapping Approach. ACM Trans. Embed. Comput. Syst. 22 (1) (2023)
Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
Energy Efficient Hardware Loop Based Optimization for CGRAs. J. Signal Process. Syst. 94 (9) (2022)
Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy
Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions. J. Signal Process. Syst. 94 (10) (2022)
Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
Hardware Based Loop Optimization for CGRA Architectures. ARC (2021)
Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy
Extended RISC-V hardware architecture for future digital communication systems. 5GWF (2021)
Hannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis. DATE (2021)
Nermine Ali, Jean-Marc Philippe, Benoît Tain, Philippe Coussy
Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators. SiPS (2021)
Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Philippe Coussy
Floating Point CGRA based Ultra-Low Power DSP Accelerator. J. Signal Process. Syst. 93 (10) (2021)
Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy
Energy Efficient Acceleration Of Floating Point Applications Onto CGRA. ICASSP (2020)
Ghita Harcha, Vianney Lapôtre, Cyrille Chavet, Philippe Coussy
Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. ISCAS (2020)
Nermine Ali, Jean-Marc Philippe, Benoît Tain, Thomas Peyret, Philippe Coussy
Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems. SiPS (2020)
Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE. DATE (2020)
Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat
Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment. DATE (2019)
Satyajit Das, Kevin J. M. Martin, Philippe Coussy
Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs. DATE (2019)
Cyrille Chavet, F. Lozachmeur, T. Barguil, A. S. Hussein, Philippe Coussy
Solving Memory Access Conflicts in LTE-4G Standard. ICASSP (2019)
Hugues Wouafo, Cyrille Chavet, Philippe Coussy
Clone-Based Encoded Neural Networks to Design Efficient Associative Memories. IEEE Trans. Neural Networks Learn. Syst. 30 (10) (2019)
Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi
A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics. ISCAS (2018)
Hugues Wouafo, Cyrille Chavet, Philippe Coussy, Robin Danilo
Efficient scalable hardware architecture for highly performant encoded neural networks. SiPS (2017)
Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec
A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (3) (2017)
Satyajit Das, Davide Rossi, Kevin J. M. Martin, Philippe Coussy, Luca Benini
A 142MOPS/mW integrated programmable array accelerator for smart visual processing. ISCAS (2017)
Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini
Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures. ASP-DAC (2017)
Awais Sani, Philippe Coussy, Cyrille Chavet
A dynamically reconfigurable ECC decoder architecture. DATE (2016)
Satyajit Das, Thomas Peyret, Kevin J. M. Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy
A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI (2016)
Robin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia, Philippe Coussy
Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection. DASIP (2016)
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani
In-place memory mapping approach for optimized parallel hardware interleaver architectures. DATE (2015)
Hugues Wouafo, Cyrille Chavet, Philippe Coussy
Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. ISCAS (2015)
Robin Danilo, Philippe Coussy, Laura Conde-Canencia, Vincent Gripon, Warren J. Gross
Restricted Clustered Neural Network for Storing Real Data. ACM Great Lakes Symposium on VLSI (2015)
Jeffrey L. Krichmar, Philippe Coussy, Nikil D. Dutt
Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible Models. ACM J. Emerg. Technol. Comput. Syst. 11 (4) (2015)
Philippe Coussy, Cyrille Chavet, Hugues Nono Wouafo, Laura Conde-Canencia
Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories. ACM J. Emerg. Technol. Comput. Syst. 11 (4) (2015)
Robin Danilo, Hooman Jarollahi, Vincent Gripon, Philippe Coussy, Laura Conde-Canencia, Warren J. Gross
Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks. ISCAS (2015)
Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec
A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators. ISCAS (2014)
Mickael Lanoe, Matteo Bordin, Dominique Heller, Philippe Coussy, Cyrille Chavet
A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code. ICECS (2014)
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures. ACM Great Lakes Symposium on VLSI (2014)
Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. ASAP (2014)
Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy
An automated design approach to map applications on CGRAs. ACM Great Lakes Symposium on VLSI (2014)
Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. ICASSP (2014)
Paolo Burgio, Andrea Marongiu, Philippe Coussy, Luca Benini
A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory. EUC (2014)
Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec
A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator. ACM Great Lakes Symposium on VLSI (2014)
Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini
A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters. DATE (2014)
Aroua Briki, Cyrille Chavet, Philippe Coussy
A memory mapping approach for network and controller optimization in parallel interleaver architectures. ACM Great Lakes Symposium on VLSI (2013)
Aroua Briki, Cyrille Chavet, Philippe Coussy
A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller. SiPS (2013)
Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo
Dynamic branch prediction for high-level synthesis. FPL (2013)
Awais Hussain Sani, Philippe Coussy, Cyrille Chavet
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. IEEE Trans. Signal Process. 61 (16) (2013)
Paolo Burgio, Andrea Marongiu, Robin Danilo, Philippe Coussy, Luca Benini
Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters. DASIP (2013)
Vianney Lapotre, Philippe Coussy, Cyrille Chavet
Introduction de la prédiction de branchement dans la synthèse de haut niveau. Tech. Sci. Informatiques 32 (2) (2013)
Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet
On-chip implementation of memory mapping algorithm to support flexible decoder architecture. ICASSP (2013)
Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang
ESL Design Methodology. J. Electr. Comput. Eng. 2012 (2012)
Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS (2012)
Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. DSD (2012)
Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin
A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI (2012)
Philippe Coussy, Dominique Heller, Cyrille Chavet
High-Level Synthesis: On the path to ESL design. ASICON (2011)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS (2011)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP (2011)
Philippe Coussy, Andrés Takach, Michael McNamara, Mike Meredith
An introduction to the SystemC synthesis subset standard. CODES+ISSS (2010)
Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin
A Design Flow for Critical Embedded Systems. SIES (2010)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS (2010)
Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures CoRR (2010)
Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL (2010)
Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet
High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Cyrille Chavet, Philippe Coussy
A memory mapping approach for parallel interleaver design with multiples read and write accesses. ISCAS (2010)
Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin
Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS (2010)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP (2010)
Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. J. Signal Process. Syst. 56 (2-3) (2009)
Philippe Coussy, Andrés Takach
Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design. IEEE Des. Test Comput. 26 (4) (2009)
Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach
An Introduction to High-Level Synthesis. IEEE Des. Test Comput. 26 (4) (2009)
Philippe Coussy, Ghizlane Lhairech-Lebreton, Dominique Heller
Multiple Word-Length High-Level Synthesis. EURASIP J. Embed. Syst. 2008 (2008)
Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system. EUSIPCO (2007)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
Constrained algorithmic IP design for system-on-chip. Integr. 40 (2) (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS (2007)
Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy
Synthesis of Multimode digital signal processing systems. AHS (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Application of a design space exploration tool to enhance interleaver generation CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Design Methodology for Space-Time Adapter CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Application of a design space exploration tool to enhance interleaver generation. EUSIPCO (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels CoRR (2007)
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD (2007)
Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
High-level synthesis under I/O Timing and Memory constraints CoRR (2006)
Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin
Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS (2006)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5 (1) (2006)
Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI CoRR (2006)
Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example]. ICASSP (5) (2005)
Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
High-level synthesis under I/O timing and memory constraints. ISCAS (1) (2005)
Lobna Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart
SystemCmantic: A high level Modelling and Co-Design Framework. FDL (2005)
Philippe Coussy, David Gnaedig, Amor Nafkha, Adel Baganne, Emmanuel Boutillon, Eric Martin
A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder. ICASSP (5) (2004)
Philippe Coussy, Adel Baganne, Eric Martin
Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC (2003)
Philippe Coussy, Adel Baganne, Eric Martin
A design methodology for integrating IP into SOC systems. CICC (2002)
Philippe Coussy, Adel Baganne, Eric Martin
Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder. ICECS (2002)
Philippe Coussy, Adel Baganne, Eric Martin
IP cores integration in DSP System-on-chip designs. EUSIPCO (2002)
Philippe Coussy, Adel Baganne, Eric Martin
A design methodology for IP integration. ISCAS (4) (2002)