Emmanuel Casseau

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 24

Top Topics

Instruction Set

Replacement Policy

Scheduling Algorithm

Top Venues

Microprocess. Microsystems

J. Syst. Archit.

Publications

Shanshan Wang, Chenglong Xiao, Emmanuel Casseau
Algorithms with improved delay for enumerating connected induced subgraphs of a large cardinality. Inf. Process. Lett. 183 (2024)
Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau
Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications. J. Syst. Archit. 134 (2023)
Baptiste Rossigneux, Inna Kucher, Vincent Lorrain, Emmanuel Casseau
Surround the Nonlinearity: Inserting Foldable Convolutional Autoencoders to Reduce Activation Footprint. ICCV (Workshops) (2023)
Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
Online fault tolerant energy-aware algorithm for CubeSats. Sustain. Comput. Informatics Syst. 38 (2023)
Van Long Nguyen Huu, Laurent d'Orazio, Emmanuel Casseau, Julien Lallet
Cache management in MASCARA-FPGA: from coalescing heuristic to replacement policy. DaMoN (2022)
Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau
Energy-Efficient Partial-Duplication Task Mapping Under Multiple DVFS Schemes. Int. J. Parallel Program. 50 (2) (2022)
Chenglong Xiao, Shanshan Wang, Wanjun Liu, Xinlin Wang, Emmanuel Casseau
An Optimal Algorithm for Enumerating Connected Convex Subgraphs in Acyclic Digraphs. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Emmanuel Casseau, Petr Dobiás, Oliver Sinnen, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alessandro Savino, Stefano Di Carlo, Maurizio Rebaudengo, Alberto Bosio
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum. VTS (2021)
Shanshan Wang, Chenglong Xiao, Emmanuel Casseau
An algorithm with improved delay for enumerating connected induced subgraphs of a large cardinality. CoRR (2021)
Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
Improving the CubeSat reliability thanks to a multiprocessor system using fault tolerant online scheduling. Microprocess. Microsystems 85 (2021)
Van Long Nguyen Huu, Laurent d'Orazio, Emmanuel Casseau, Julien Lallet
MASCARA-FPGA cooperation model: Query Trimming through accelerators. SSDBM (2021)
Minyu Cui, Angeliki Kritikakou, Lei Mo, Emmanuel Casseau
Fault-Tolerant Mapping of Real-Time Parallel Applications under multiple DVFS schemes. RTAS (2021)
Van Long Nguyen Huu, Julien Lallet, Emmanuel Casseau, Laurent d'Orazio
MASCARA (ModulAr Semantic CAching fRAmework) towards FPGA Acceleration for IoT Security Monitoring. Open J. Internet Things 6 (1) (2020)
Minyu Cui, Lei Mo, Angeliki Kritikakou, Emmanuel Casseau
Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints. SAMOS (2020)
Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
Fault-Tolerant Online Scheduling Algorithms for CubeSats. PARMA-DITAM@HiPEAC (2020)
Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
Evaluation of Fault Tolerant Online Scheduling Algorithms for CubeSats. DSD (2020)
Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys, Emmanuel Casseau
Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors. DASIP (2019)
Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems. DASIP (2018)
Petr Dobiás, Emmanuel Casseau, Oliver Sinnen
Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup Approach-Based Scheduling on Embedded Systems. SCOPES (2018)
Chenglong Xiao, Shanshan Wang, Wanjun Liu, Emmanuel Casseau
Parallel custom instruction identification for extensible processors. J. Syst. Archit. 76 (2017)
Imran Wali, Emmanuel Casseau, Arnaud Tisserand
An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy. DASIP (2017)
Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau
A comparison of heuristic algorithms for custom instruction selection. Microprocess. Microsystems 45 (2016)
Mai-Thanh Tran, Matthieu Gautier, Emmanuel Casseau
On the FPGA-Based Implementation of a Flexible Waveform from a High-Level Description: Application to LTE FFT Case Study. CrownCom (2016)
Mai-Thanh Tran, Emmanuel Casseau, Matthieu Gautier
Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard. DASIP (2016)
Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs. J. Signal Process. Syst. 80 (1) (2015)
Kevin J. M. Martin, Yvan Eustache, Jean-Philippe Diguet, Thanh Dinh Ngo, Emmanuel Casseau, Yaset Oliva
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms. DASIP (2015)
Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau, Xiao Yang
Selecting most profitable instruction-set extensions using ant colony heuristic. DASIP (2015)
Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau
Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m). ISVLSI (2015)
Chenglong Xiao, Emmanuel Casseau, Shanshan Wang, Wanjun Liu
Automatic custom instruction identification for application-specific instruction set processors. Microprocess. Microsystems 38 (8) (2014)
Yaset Oliva, Emmanuel Casseau, Kevin J. M. Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin, Laurent Morin
Orcc's compa-backend demonstration. DASIP (2014)
Hervé Yviquel, Alexandre Sanchez, Pekka Jääskeläinen, Jarmo Takala, Mickaël Raulet, Emmanuel Casseau
Efficient software synthesis of dynamic dataflow programs. ICASSP (2014)
Quang Hoa Le, Emmanuel Casseau, Antoine Courtay
Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture. ReConFig (2014)
Chenglong Xiao, Emmanuel Casseau
Improving high-level synthesis effectiveness through custom operator identification. ISCAS (2014)
Hervé Yviquel, Jani Boutellier, Mickaël Raulet, Emmanuel Casseau
Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. Signal Process. Image Commun. 28 (10) (2013)
Hervé Yviquel, Emmanuel Casseau, Mickaël Raulet, Pekka Jääskeläinen, Jarmo Takala
Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms. ISPA (2013)
Erwan Raffin, Christophe Wolinski, François Charot, Emmanuel Casseau, Antoine Floch, Krzysztof Kuchcinski, Stéphane Chevobbe, Stéphane Guyetant
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia Architecture. Int. J. Embed. Real Time Commun. Syst. 3 (1) (2012)
Chenglong Xiao, Emmanuel Casseau
Exact custom instruction enumeration for extensible processors. Integr. 45 (3) (2012)
Emmanuel Casseau, Bertrand Le Gal
Design of multi-mode application-specific cores based on high-level synthesis. Integr. 45 (1) (2012)
Chenglong Xiao, Emmanuel Casseau
Efficient maximal convex custom instruction enumeration for extensible processors. DASIP (2011)
Bertrand Le Gal, Emmanuel Casseau
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. J. Signal Process. Syst. 62 (3) (2011)
Hervé Yviquel, Emmanuel Casseau, Matthieu Wipliez, Mickaël Raulet
Efficient multicore scheduling of dataflow process networks. SiPS (2011)
Chenglong Xiao, Emmanuel Casseau
An efficient algorithm for custom instruction enumeration. ACM Great Lakes Symposium on VLSI (2011)
Daniel Ménard, Hai-Nam Nguyen, François Charot, Stéphane Guyetant, Jérémie Guillot, Erwan Raffin, Emmanuel Casseau
Exploiting reconfigurable SWP operators for multimedia applications. ICASSP (2011)
Andrei Banciu, Emmanuel Casseau, Daniel Ménard, Thierry Michel
Stochastic modeling for floating-point to fixed-point conversion. SiPS (2011)
Chenglong Xiao, Emmanuel Casseau
Efficient custom instruction enumeration for extensible processors. ASAP (2011)
Bertrand Le Gal, Emmanuel Casseau
Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design. EURASIP J. Adv. Signal Process. 2011 (2011)
Andrei Banciu, Emmanuel Casseau, Daniel Ménard, Thierry Michel
A case study of the stochastic modeling approach for range estimation. DASIP (2010)
Cecile Beaumin, Olivier Sentieys, Emmanuel Casseau, Arnaud Carer
A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design. DASIP (2010)
Erwan Raffin, Christophe Wolinski, François Charot, Krzysztof Kuchcinski, Stéphane Guyetant, Stéphane Chevobbe, Emmanuel Casseau
Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture. DASIP (2010)
Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet
High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Daniel Ménard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David
Reconfigurable Operator Based Multimedia Embedded Processor. ARC (2009)
Bertrand Le Gal, Emmanuel Casseau
Automated multimode system design for high performance DSP applications. EUSIPCO (2009)
Shafqat Khan, Emmanuel Casseau, Daniel Ménard
Reconfigurable SWP Operator for Multimedia Processing. ASAP (2009)
Emmanuel Casseau, Bertrand Le Gal
High-level synthesis for the design of FPGA-based signal processing systems. ICSAMOS (2009)
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 16 (11) (2008)
Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau. Tech. Sci. Informatiques 27 (9-10) (2008)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
Constrained algorithmic IP design for system-on-chip. Integr. 40 (2) (2007)
Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy
Synthesis of Multimode digital signal processing systems. AHS (2007)
Bertrand Le Gal, Lilian Bossuet, Shafqat Khan, Emmanuel Casseau
HLS design flow for the synthesis of multimode systems under multiple constraints. ICECS (2007)
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD (2007)
Sylvain Huet, Sebastien Le Nours, Olivier Pasquier, Emmanuel Casseau
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. FDL (2007)
Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. DSD (2006)
Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems. SoCC (2006)
Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. SiPS (2006)
Bertrand Le Gal, Emmanuel Casseau
IP Generation Targeting Multiple Bit-Width Standards. ICECS (2006)
Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin
G729 Voice Decoder Design. J. VLSI Signal Process. 42 (2) (2006)
Sylvain Huet, Emmanuel Casseau, Olivier Pasquier, Sebastien Le Nours
Hardware Communication Refinement in Digital Signal Processing. FDL (2006)
Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embed. Comput. Syst. 5 (1) (2006)
Guillaume Savaton, Emmanuel Casseau, Eric Martin
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. Signal Process. 86 (7) (2006)
Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. IEEE International Workshop on Rapid System Prototyping (2005)
Emmanuel Casseau, Bertrand Le Gal, Pierre Bomel, Christophe Jégo, Sylvain Huet, Eric Martin
C-based rapid prototyping for digital signal processing. EUSIPCO (2005)
Bertrand Le Gal, Emmanuel Casseau, Eric Martin
Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses. EUSIPCO (2005)
Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno
Hardware Virtual Components Compliant with Communication System Standards. DSD (2005)
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. ISVLSI (2005)
Emmanuel Casseau, Christophe Jégo, Eric Martin
Synthèse architecturale d'applications temps réel pour technologies submicroniques. Tech. Sci. Informatiques 23 (1) (2004)
Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin
Reed-Solomon behavioral virtual component for communication systems. ISCAS (4) (2004)
Emmanuel Casseau
SoC design using behavioral level virtual components. ICECS (2002)
Emmanuel Casseau, Christophe Jégo, Eric Martin
Architectural synthesis of digital signal processing applications dedicated to submicron technologies. ICECS (2001)
Christophe Jégo, Emmanuel Casseau, Eric Martin
Architectural Synthesis with Interconnection Cost Control. VLSI (1999)
Emmanuel Casseau, Eric Lüthi
Architecture of a high-rate VLSI Viterbi decoder. ICECS (1996)
Eric Lüthi, Emmanuel Casseau
High Rate Soft Output Viterbi Decoder. ED&TC (1996)
Emmanuel Casseau, Dominique Degrugillier
A Linear Systolic Array for LU Decomposition. VLSI Design (1994)