Cyrille Chavet

ORCID

Publication Activity (10 Years)

Years Active: 2007-2021
Publications (10 Years): 10

Top Venues

ICASSP

SiPS

ACM Great Lakes Symposium on VLSI

DATE

University of Southern Brittany, Morbihan, France (PHD)

Education History

University of Southern Brittany, Morbihan, France

PHD

Publications

Maël Tourres, Cyrille Chavet, Bertrand Le Gal, Jérémie Crenne, Philippe Coussy
Extended RISC-V hardware architecture for future digital communication systems. 5GWF (2021)
Hassan Harb, Cyrille Chavet
Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards. J. Signal Process. Syst. 93 (10) (2021)
Hassan Harb, Cyrille Chavet
Fully Parallel Circular-Shift Rotation Network for Communication Standards. IEEE Trans. Circuits Syst. (12) (2020)
Hassan Harb, Cyrille Chavet
Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards. ICASSP (2020)
Ghita Harcha, Vianney Lapôtre, Cyrille Chavet, Philippe Coussy
Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. ISCAS (2020)
Cyrille Chavet, F. Lozachmeur, T. Barguil, A. S. Hussein, Philippe Coussy
Solving Memory Access Conflicts in LTE-4G Standard. ICASSP (2019)
Hugues Wouafo, Cyrille Chavet, Philippe Coussy
Clone-Based Encoded Neural Networks to Design Efficient Associative Memories. IEEE Trans. Neural Networks Learn. Syst. 30 (10) (2019)
Hugues Wouafo, Cyrille Chavet, Philippe Coussy, Robin Danilo
Efficient scalable hardware architecture for highly performant encoded neural networks. SiPS (2017)
Awais Sani, Philippe Coussy, Cyrille Chavet
A dynamically reconfigurable ECC decoder architecture. DATE (2016)
Robin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia, Philippe Coussy
Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection. DASIP (2016)
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani
In-place memory mapping approach for optimized parallel hardware interleaver architectures. DATE (2015)
Hugues Wouafo, Cyrille Chavet, Philippe Coussy
Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. ISCAS (2015)
Philippe Coussy, Cyrille Chavet, Hugues Nono Wouafo, Laura Conde-Canencia
Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories. ACM J. Emerg. Technol. Comput. Syst. 11 (4) (2015)
Mickael Lanoe, Matteo Bordin, Dominique Heller, Philippe Coussy, Cyrille Chavet
A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code. ICECS (2014)
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures. ACM Great Lakes Symposium on VLSI (2014)
Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. ICASSP (2014)
Aroua Briki, Cyrille Chavet, Philippe Coussy
A memory mapping approach for network and controller optimization in parallel interleaver architectures. ACM Great Lakes Symposium on VLSI (2013)
Aroua Briki, Cyrille Chavet, Philippe Coussy
A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller. SiPS (2013)
Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo
Dynamic branch prediction for high-level synthesis. FPL (2013)
Awais Hussain Sani, Philippe Coussy, Cyrille Chavet
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. IEEE Trans. Signal Process. 61 (16) (2013)
Vianney Lapotre, Philippe Coussy, Cyrille Chavet
Introduction de la prédiction de branchement dans la synthèse de haut niveau. Tech. Sci. Informatiques 32 (2) (2013)
Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet
On-chip implementation of memory mapping algorithm to support flexible decoder architecture. ICASSP (2013)
Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS (2012)
Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. DSD (2012)
Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin
A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI (2012)
Philippe Coussy, Dominique Heller, Cyrille Chavet
High-Level Synthesis: On the path to ESL design. ASICON (2011)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS (2011)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP (2011)
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS (2010)
Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard
Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures CoRR (2010)
Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet
High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Cyrille Chavet, Philippe Coussy
A memory mapping approach for parallel interleaver design with multiples read and write accesses. ISCAS (2010)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP (2010)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Application of a design space exploration tool to enhance interleaver generation CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A Design Methodology for Space-Time Adapter CoRR (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Application of a design space exploration tool to enhance interleaver generation. EUSIPCO (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI (2007)
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels CoRR (2007)
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
A design flow dedicated to multi-mode architectures for DSP applications. ICCAD (2007)

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Publication Activity (10 Years)

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Cyrille Chavet