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A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm.
Awais Hussain Sani
Philippe Coussy
Cyrille Chavet
Published in:
IEEE Trans. Signal Process. (2013)
Keyphrases
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worst case
parallel implementation
memory space
optimal solution
computational complexity
high speed
memory requirements
learning algorithm
k means
memory usage
objective function
np hard
vlsi implementation
approximation ratio
search space
approximation algorithms
low cost