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Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.

Saeed-ur RehmanAwais SaniCyrille ChavetPhilippe Coussy
Published in: ICASSP (2014)
Keyphrases
  • routing algorithm
  • memory subsystem
  • memory management
  • shortest path
  • ad hoc networks
  • real time
  • computational complexity
  • low cost