Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis.

Bertrand Le Gal Emmanuel Casseau

Published in: J. Signal Process. Syst. (2011)

Keyphrases

hardware design
high level synthesis
hardware implementation
parallel architecture
signal processing
digital signal processing
fpga hardware
field programmable gate array
design space exploration
image processing
data analysis
graphical models
parallel processing
shared memory