Daniel D. Gajski

Publication Activity (10 Years)

Years Active: 1978-2014
Publications (10 Years): 0

Top Topics

Image Processing

Orientation Estimation

Hierarchical Organization

Bayesian Networks

Top Venues

Publications

Kyoungwon Kim, Daniel D. Gajski
Hierarchy-Aware mapping of pipelined applications. MWSCAS (2014)
Kyoungwon Kim, Daniel D. Gajski
Trace-Driven Performance Estimation of multi-core platforms. MWSCAS (2014)
Jelena Trajkovic, Samar Abdi, Gabriela Nicolescu, Daniel D. Gajski
Automated Generation of Custom Processor Core from C Code. J. Electr. Comput. Eng. 2012 (2012)
Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski
Automatic TLM Generation for Early Validation of Multicore Systems. IEEE Des. Test Comput. 28 (3) (2011)
Yonghyun Hwang, Gunar Schirner, Samar Abdi, Daniel D. Gajski
Accurate timed RTOS model for transaction level modeling. DATE (2010)
Jelena Trajkovic, Daniel D. Gajski
Early performance-cost estimation of application-specific data path pipelining. SASP (2010)
Samar Abdi, Yonghyun Hwang, Lochi Yu, Hansu Cho, Ines Viskic, Daniel D. Gajski
Embedded system environment: A framework for TLM-based design and prototyping. International Symposium on Rapid System Prototyping (2010)
Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach
An Introduction to High-Level Synthesis. IEEE Des. Test Comput. 26 (4) (2009)
Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, Jürgen Teich
Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (10) (2009)
Jelena Trajkovic, Daniel D. Gajski
Custom Processor Core Construction from C Code. SASP (2008)
Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Embed. Syst. 2008 (2008)
Daniel D. Gajski, Samar Abdi, Ines Viskic
Model Based Synthesis of Embedded Software. SEUS (2008)
Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil
TLM: Crossing Over From Buzz To Adoption. DAC (2007)
Ines Viskic, Samar Abdi, Daniel D. Gajski
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. LCTES (2007)
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
An Interactive Design Environment for C-based High-Level Synthesis. IESS (2007)
Daniel D. Gajski
New Strategies for System-Level Design. DDECS (2007)
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski
Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS (2006)
Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski
Designing a custom architecture for DCT using NISC technology. ASP-DAC (2006)
Samar Abdi, Daniel D. Gajski
Functional Validation of System Level Static Scheduling. DATE (2005)
Shuqing Zhao, Daniel D. Gajski
Defining an Enhanced RTL Semantics. DATE (2005)
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
Automatic network generation for system-on-chip communication design. CODES+ISSS (2005)
Bita Gorjiara, Daniel D. Gajski
Custom Processor Design Using NISC: A Case-Study on DCT algorithm. ESTIMedia (2005)
Haobo Yu, Rainer Dömer, Daniel D. Gajski
Software and Driver Synthesis from Transaction Level Models. IESS (2005)
Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski
Automatic Generation of Communication Architectures. IESS (2005)
Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski
System-level communication modeling for network-on-chip synthesis. ASP-DAC (2005)
Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. ICCD (2005)
Shuqing Zhao, Daniel D. Gajski
Structural operational semantics for supporting multi-cycle operations in RTL HDLs. MEMOCODE (2005)
Jianwen Zhu, Daniel D. Gajski
An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer
Seamless approach for the design of control systems for power electronics and electric drives. SMC (2002)
Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer
Co-design of embedded controllers for power electronics and electric systems. ISIC (2002)
Smita Bakshi, Daniel D. Gajski
Partitioning and pipelining for performance-constrained hardware/software systems. IEEE Trans. Very Large Scale Integr. Syst. 7 (4) (1999)
Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. Very Large Scale Integr. Syst. 6 (1) (1998)
Smita Bakshi, Daniel D. Gajski
Hierarchical pipelining for behaviors, loops, and operations. ICCD (1998)
Rainer Dömer, Daniel D. Gajski, Jianwen Zhu
Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. 40 (3) (1998)
Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski
A quantitative analysis for optimizing memory allocation. ASP-DAC (1997)
Smita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan
Component selection in resource shared and pipelined DSP applications. EURO-DAC (1996)
Jie Gong, Daniel D. Gajski, Smita Bakshi
Model Refinement for Hardware-Software Codesign. ED&TC (1996)
Smita Bakshi, Daniel D. Gajski
Component selection for high-performance pipelines. IEEE Trans. Very Large Scale Integr. Syst. 4 (2) (1996)
Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung
System design methodologies: aiming at the 100 h design cycle. IEEE Trans. Very Large Scale Integr. Syst. 4 (1) (1996)
Sanjiv Narayan, Daniel D. Gajski
Rapid performance estimation for system design. EURO-DAC (1996)
Hsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski
Clock optimization for high-performance pipelined design. EURO-DAC (1996)
Frank Vahid, Daniel D. Gajski
Incremental hardware estimation during hardware/software functional partitioning. IEEE Trans. Very Large Scale Integr. Syst. 3 (3) (1995)
Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (6) (1995)
Jie Gong, Daniel D. Gajski, Sanjiv Narayan
Software estimation using a generic-processor model. ED&TC (1995)
Jie Gong, Daniel D. Gajski, Alexandru Nicolau
Performance evaluation for application-specific architectures. IEEE Trans. Very Large Scale Integr. Syst. 3 (4) (1995)
Smita Bakshi, Daniel D. Gajski
A memory selection algorithm for high-performance pipelines. EURO-DAC (1995)
Frank Vahid, Daniel D. Gajski
SLIF: a specification-level intermediate format for system design. ED&TC (1995)
Frank Vahid, Daniel D. Gajski
Closeness metrics for system-level functional partitioning. EURO-DAC (1995)
Nancy D. Holmes, Daniel D. Gajski
Architectural exploration for datapaths with memory hierarchy. ED&TC (1995)
Daniel D. Gajski, Frank Vahid
Specification and Design of Embedded Hardware-Software Systems. IEEE Des. Test Comput. 12 (1) (1995)
Frank Vahid, Daniel D. Gajski
Clustering for improved system-level functional partitioning. ISSS (1995)
Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski
Condition graphs for high-quality behavioral synthesis. ICCAD (1994)
Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung
100-hour design cycle: a test case. EURO-DAC (1994)
Jie Gong, Daniel D. Gajski, Alex Nicolau
A performance evaluator for parameterized ASIC architectures. EURO-DAC (1994)
Daniel D. Gajski, Loganath Ramachandran
Introduction to High-Level Synthesis. IEEE Des. Test Comput. 11 (4) (1994)
Frank Vahid, Daniel D. Gajski, Sanjiv Narayan
A transformation for integrating VHDL behavioral specification with synthesis and software generation. EURO-DAC (1994)
Frank Vahid, Daniel D. Gajski, Jie Gong
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. EURO-DAC (1994)
Smita Bakshi, Daniel D. Gajski
A component selection algorithm for high-performance pipelines. EURO-DAC (1994)
Smita Bakshi, Daniel D. Gajski
Design exploration for high-performance pipelines. ICCAD (1994)
Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (4) (1994)
Elke A. Rundensteiner, Daniel D. Gajski, Lubomir Bic
Component synthesis from functional descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (9) (1993)
Sanjiv Narayan, Daniel D. Gajski
Features supporting system-level specification in HDLs. EURO-DAC (1993)
Loganath Ramachandran, Daniel D. Gajski
Architectural tradeoffs in synthesis of pipelined controls. EURO-DAC (1993)
Hsiao-Ping Juan, Nancy D. Holmes, Smita Bakshi, Daniel D. Gajski
Top-down modeling of RISC processors in VHDL. EURO-DAC (1993)
Loganath Ramachandran, Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
Synthesis of functions and procedures in behavioral VHDL. EURO-DAC (1993)
Sanjiv Narayan, Daniel D. Gajski
System clock estimation based on clock slack minimization. EURO-DAC (1992)
Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski
Timing models for high-level synthesis. EURO-DAC (1992)
Loganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
Semantics and synthesis of signals in behavioral VHDL. EURO-DAC (1992)
Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
System Level Specification and Synthesis. VLSI Design (1992)
Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
System Specification with the SpecCharts Language. IEEE Des. Test Comput. 9 (4) (1992)
Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu
Layout placement for sliced architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (1) (1992)
Allen C.-H. Wu, Daniel D. Gajski
Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (4) (1992)
Allen C.-H. Wu, Daniel D. Gajski
Glue-logic partitioning for floorplans with a rectilinear datapath. EURO-DAC (1991)
Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
Translating system specifications to VHDL. EURO-DAC (1991)
James R. Kipps, Daniel D. Gajski
The Role of Learning in Logic Synthesis. Int. J. Pattern Recognit. Artif. Intell. 4 (2) (1990)
Forrest Brewer, Daniel D. Gajski
Chippe: a system for constraint driven behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (7) (1990)
Nikil D. Dutt, Daniel D. Gajski
Design Synthesis and Silicon Compilation. IEEE Des. Test Comput. 7 (6) (1990)
Min-You Wu, Daniel D. Gajski
Computer-aided programming for message-passing systems: problems and solutions. Proc. IEEE 77 (12) (1989)
James R. Kipps, Daniel D. Gajski
The role of learning in logic synthesis. TAI (1989)
Joseph Lis, Daniel D. Gajski
Synthesis from VHDL. ICCD (1988)
Chidchanok Lursinsap, Daniel D. Gajski
A technique for pull-up transistor folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (8) (1988)
Min-You Wu, Daniel D. Gajski
A programming aid for hypercube architectures. J. Supercomput. 2 (3) (1988)
Youn-Long Lin, Daniel D. Gajski
LES: a layout expert system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (8) (1988)
Barry M. Pangrle, Daniel D. Gajski
Design Tools for Intelligent Silicon Compilation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (6) (1987)
Steven T. Healey, Daniel D. Gajski
Decomposition of logic networks into silicon. DAC (1985)
Vijay K. Raj, Barry M. Pangrle, Daniel D. Gajski
Microprocessor synthesis. DAC (1984)
Daniel D. Gajski, Duncan H. Lawrie, David J. Kuck, Ahmed H. Sameh
Cedar. COMPCON (1984)
Daniel D. Gajski
Silicon compilers and expert systems for VLSI. DAC (1984)
Daniel D. Gajski, Ahmed H. Sameh, John A. Wisniewski
Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor. ICPP (1982)
Avinoam Bilgory, Daniel D. Gajski
Automatic generation of cells for recurrence structures. DAC (1981)
Albert E. Casavant, Daniel D. Gajski, David J. Kuck
Automatic design with dependence graphs. DAC (1980)
Daniel D. Gajski, Louis P. Rubinfield
Design of arithmetic elements for Burroughs Scientific Processor. IEEE Symposium on Computer Arithmetic (1978)