Allen C.-H. Wu

Publication Activity (10 Years)

Years Active: 1990-2021
Publications (10 Years): 7

Top Topics

Privacy Guarantees

Secure Multiparty Computation

Learning Scheme

Horizontally Partitioned

Top Venues

Comput. Electr. Eng.

Publications

Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
A novel privacy-preserving deep learning scheme without a cryptography component. Comput. Electr. Eng. 94 (2021)
Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). ASP-DAC (2021)
Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. SoCC (2019)
Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang
Crosstalk-aware TSV-buffer Insertion in 3D IC. SoCC (2019)
Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang
A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. CoRR (2019)
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE (2016)
Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
Performance-driven crosstalk elimination at post-compiler level. ISCAS (2006)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11 (4) (2006)
Bing-Fei Wu, Chuan-Tsai Lin, Chao-Jung Chen, Tze-Chiuan Lai, Hsueh-Lung Liao, Allen C.-H. Wu
A fast lane and vehicle detection approach for autonomous vehicles. SIP (2005)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) (2005)
Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
Decomposition of Instruction Decoder for Low Power Design. DATE (2004)
Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE (2003)
Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE (2003)
J. C.-Y. Kao, C.-F. Su, Allen C.-H. Wu
High-performance FIR generation based on a timing-driven architecture and component selection method. ISCAS (4) (2002)
M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu
A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. ISCAS (1) (2002)
Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu
An RTL design-space exploration method for high-level applications. ASP-DAC (2001)
Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud
Embedded tutorial: essential issues for IP reuse. ASP-DAC (2000)
Chien-Chu Kuo, Allen C.-H. Wu
Delay Budgeting for a Timing-Closure-Driven Design Method. ICCAD (2000)
Chi-Hong Hwang, Allen C.-H. Wu
A predictive system shutdown method for energy saving of event-driven computation. ACM Trans. Design Autom. Electr. Syst. 5 (2) (2000)
Wen-Jong Fang, Allen C.-H. Wu
Multiway FPGA partitioning by fully exploiting design hierarchy. ACM Trans. Design Autom. Electr. Syst. 5 (1) (2000)
Allen C.-H. Wu, Nikil D. Dutt
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). IEEE Trans. Very Large Scale Integr. Syst. 8 (5) (2000)
Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
EmGen-a module generator for logic emulation applications. IEEE Trans. Very Large Scale Integr. Syst. 7 (4) (1999)
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC (1999)
Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu
A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. ASP-DAC (1999)
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (4) (1999)
Kun-Ming Ho, Allen C.-H. Wu
Module Generation of High Performance FPGA-Based Multipliers. FPGA (1999)
Wen-Jong Fang, Allen C.-H. Wu
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. IEEE Des. Test Comput. 15 (2) (1998)
Wen-Jong Fang, Allen C.-H. Wu
Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. DAC (1998)
Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD (1998)
Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
Module Generation of Complex Macros for Logic-Emulation Applications. FPGA (1997)
Allen C.-H. Wu
Datapath Optimization Using Layout Information: An Empirical Study. VLSI Design 5 (2) (1997)
Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin
Preserving HDL synthesis hierarchy for cell placement. ISPD (1997)
Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. DAC (1997)
Wen-Jong Fang, Allen C.-H. Wu
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. DAC (1997)
Wen-Jong Fang, Allen C.-H. Wu
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (10) (1997)
Wei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu
Evaluating cost-performance tradeoffs for system level applications. ASP-DAC (1997)
Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu
Scheduling techniques for variable voltage low power designs. ACM Trans. Design Autom. Electr. Syst. 2 (2) (1997)
Yuh-Sheng Lee, Allen C.-H. Wu
A performance and routability-driven router for FPGAs considering path delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (2) (1997)
Chi-Hong Hwang, Allen C.-H. Wu
An entropy measure for power estimation of Boolean functions. ASP-DAC (1997)
Chi-Hong Hwang, Allen C.-H. Wu
A predictive system shutdown method for energy saving of event-driven computation. ICCAD (1997)
Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin
DP-Gen: a datapath generator for multiple-FPGA applications. ASP-DAC (1997)
Wen-Jong Fang, Allen C.-H. Wu
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. ICCAD (1996)
Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu
The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications. Softw. Pract. Exp. 26 (10) (1996)
Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee
EMPAR: an interactive synthesis environment for hardware emulations. ASP-DAC (1995)
Yuh-Sheng Lee, Allen C.-H. Wu
A Performance and Routability Driven Router for FPGAs Considering Path Delays. DAC (1995)
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (9) (1995)
Allen C.-H. Wu, Youn-Long Lin
High-Level Synthesis -A Tutorial. IEICE Trans. Inf. Syst. (3) (1995)
Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin
TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (3) (1995)
Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC (1994)
Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
State Assignment for Power and Area Minimization. ICCD (1994)
Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (4) (1994)
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD (1993)
Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
An effective methodology for functional pipelining. ICCAD (1992)
Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul
Accurate layout area and delay modeling for system level design. ICCAD (1992)
Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski
Timing models for high-level synthesis. EURO-DAC (1992)
Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu
Layout placement for sliced architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (1) (1992)
Allen C.-H. Wu, Tedd Hadley, Daniel Gajski
An efficient multi-view design model for real-time interactive synthesis. ICCAD (1992)
Allen C.-H. Wu, Daniel D. Gajski
Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (4) (1992)
Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski
Layout-Area Models for High-Level Synthesis. ICCAD (1991)
Allen C.-H. Wu, Daniel D. Gajski
Glue-logic partitioning for floorplans with a rectilinear datapath. EURO-DAC (1991)
Allen C.-H. Wu, Daniel Gajski
Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ICCAD (1990)
Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski
A new algorithm for transistor sizing in CMOS circuits. EURO-DAC (1990)