Champaka Ramachandran

Publication Activity (10 Years)

Years Active: 1991-1994
Publications (10 Years): 0

Publications

Champaka Ramachandran, Fadi J. Kurdahi
Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (12) (1994)
Champaka Ramachandran, Fadi J. Kurdahi
Incorporating the Controller Effects During Register Transfer Level Synthesis. EDAC-ETC-EUROASIC (1994)
Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran
On the intrinsic Rent parameter and spectra-based partitioning methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (1) (1994)
Yulin Chen, Wei Kang Tsai, Fadi J. Kurdahi, Tzong-Dar Her, Champaka Ramachandran
A performance driven logic synthesis system using delay estimator. Great Lakes Symposium on VLSI (1994)
Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi
An Empirical Study on the Effects of Physical Design in High-Level Synthesis. VLSI Design (1994)
Fadi J. Kurdahi, Champaka Ramachandran
Evaluating layout area tradeoffs for high level applications. IEEE Trans. Very Large Scale Integr. Syst. 1 (1) (1993)
Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul
Accurate layout area and delay modeling for system level design. ICCAD (1992)
Champaka Ramachandran, Fadi J. Kurdahi
Combined topological and functionality based delay estimation using a layout-driven approach for high level applications. EURO-DAC (1992)
Lars W. Hagen, Fadi J. Kurdahi, Champaka Ramachandran, Andrew B. Kahng
On the intrinsic rent parameter and spectra-based partitioning methodologies. EURO-DAC (1992)
Fadi J. Kurdahi, Champaka Ramachandran
LAST: a Layout Area and Shape function esTimator for high level applications. EURO-DAC (1991)