Decomposition of Instruction Decoder for Low Power Design.

Wu-An Kuo TingTing Hwang Allen C.-H. Wu

Published in: DATE (2004)

Keyphrases

low power
low cost
single chip
low power consumption
vlsi architecture
high speed
power consumption
logic circuits
cmos technology
gate array
power dissipation
digital signal processing
low complexity
power reduction
motion estimation
wireless transmission
high power
mixed signal