Jianwen Zhu

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 6

Top Topics

Stochastic Control

Top Venues

ACM Trans. Storage

Sci. China Inf. Sci.

Publications

Jianwen Zhu, Hao Zhang, Sibo Zhao, Weimin Bao
Multi-constrained intelligent gliding guidance via optimal control and DQN. Sci. China Inf. Sci. 66 (3) (2023)
Reza Nakhjavani, Jianwen Zhu
Rotary Register File: A Micro-Architectural Primitive on FPGA. FCCM (2020)
Shu-Yi Jack Wong, Jianwen Zhu
A fast Bayesian algorithmic enhancement for real time bit error ratio test (BERT). GlobalSIP (2017)
Reza Nakhjavani, Jianwen Zhu
A Case for Common-Case: On FPGA Acceleration of Erasure Coding. FCCM (2017)
Yue Yang, Jianwen Zhu
Write Amplification with Write Skew. MASCOTS (2016)
Yue Yang, Jianwen Zhu
Write Skew and Zipf Distribution: Evidence and Implications. ACM Trans. Storage 12 (4) (2016)
Canwen Xiao, Yue Yang, Jianwen Zhu
A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks. IEEE Comput. Archit. Lett. 14 (2) (2015)
Yue Yang, Jianwen Zhu
Algebraic modeling of write amplification in hotness-aware SSD. SYSTOR (2015)
Yue Yang, Jianwen Zhu
Analytical modeling of garbage collection algorithms in hotness-aware flash-based solid state drives. MSST (2014)
Zefu Dai, Jianwen Zhu
Saturating the transceiver bandwidth: switch fabric design on FPGAs. FPGA (2012)
Yi Ni, Wai Sum Mong, Jianwen Zhu
On virtual prototyping of embedded system-on-chips. ASICON (2011)
Xun Chen, Jianwen Zhu
Regular fabric for regular FPGA (abstract only). FPGA (2011)
Xun Chen, Jianwen Zhu, Minxuan Zhang
Timing-Driven Routing of High Fanout Nets. FPL (2011)
Rami Beidas, Wai Sum Mong, Jianwen Zhu
Register pressure aware scheduling for high level synthesis. ASP-DAC (2011)
Zefu Dai, Jianwen Zhu
A bursty multi-port memory controller with quality-of-service guarantees. CODES+ISSS (2011)
Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu
Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (1) (2011)
Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu
Using variable clocking to reduce leakage in synchronous circuits. ICCD (2010)
Huimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu
Towards scalable placement for FPGAs. FPGA (2010)
Alexander Choong, Rami Beidas, Jianwen Zhu
Parallelizing Simulated Annealing-Based Placement Using GPGPU. FPL (2010)
Zefu Dai, Nick Ni, Jianwen Zhu
A 1 cycle-per-byte XML parsing accelerator. FPGA (2010)
Silvian Calman, Jianwen Zhu
Interprocedural induction variable analysis based on interprocedural SSA form IR. PASTE (2010)
Zefu Dai, Mark Jarvin, Jianwen Zhu
Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees. ICCAD (2010)
Silvian Calman, Jianwen Zhu
Increasing the Scope and Resolution of Interprocedural Static Single Assignment. SAS (2009)
Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
Towards automated ECOs in FPGAs. FPGA (2009)
Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu
VariPipe: Low-overhead variable-clock synchronous pipelines. ICCD (2009)
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI (2008)
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC (2007)
Bin Wu, Jianwen Zhu, Farid N. Najm
Dynamic-range estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Qianying Tang, Jianwen Zhu
Two-Dimensional Layout Migration by Soft Constraint Satisfaction. ISQED (2005)
Jianwen Zhu, Fang Fang, Qianying Tang
Calligrapher: a new layout-migration engine for hard intellectual property libraries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Bin Wu, Jianwen Zhu, Farid N. Najm
A non-parametric approach for dynamic range estimation of nonlinear systems. DAC (2005)
Rami Beidas, Jianwen Zhu
Scalable interprocedural register allocation for high level synthesis. ASP-DAC (2005)
Jianwen Zhu, Silvian Calman
Context sensitive symbolic pointer analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Jianwen Zhu
Towards scalable flow and context sensitive pointer analysis. DAC (2005)
Dennis Wu, Jianwen Zhu
BDD-based two variable sharing extraction. ASP-DAC (2005)
Bin Wu, Jianwen Zhu, Farid N. Najm
Dynamic range estimation for nonlinear systems. ICCAD (2004)
Khushwinder Jasrotia, Jianwen Zhu
Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis. ISQED (2004)
Massimo Poncino, Jianwen Zhu
DynamoSim: a trace-based dynamically compiled instruction set simulator. ICCAD (2004)
Bin Wu, Jianwen Zhu, Farid N. Najm
An analytical approach for dynamic range estimation. DAC (2004)
Rami Beidas, Jianwen Zhu
A queuing-theoretic performance model for context-flow system-on-chip platforms. ESTIMedia (2004)
Fang Fang, Jianwen Zhu
Automatic process migration of datapath hard IP libraries. ASP-DAC (2004)
Fang Fang, Jianwen Zhu
Calligrapher: A New Layout Migration Engine Based on Geometric Closeness. ISQED (2004)
Jianwen Zhu, Silvian Calman
Symbolic pointer analysis revisited. PLDI (2004)
Zhong Wang, Jianwen Zhu
Piecewise quadratic waveform matching with successive chord iteration. ASP-DAC (2004)
Jianwen Zhu, Wai Sum Mong
Specification of Non-Functional Intellectual Property Components. DATE (2003)
Zhong Wang, Jianwen Zhu
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching. DATE (2003)
Wai Sum Mong, Jianwen Zhu
A retargetable micro-architecture simulator. DAC (2003)
Rami Beidas, Jianwen Zhu
Performance Efficiency of Context-Flow System-on-Chip Platform. ICCAD (2003)
Maghsoud Abbaspour, Jianwen Zhu
Retargetable binary utilities. DAC (2002)
Jianwen Zhu
Symbolic pointer analysis. ICCAD (2002)
Jianwen Zhu, Daniel D. Gajski
An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Khushwinder Jasrotia, Jianwen Zhu
Hardware Implementation of a Memory Allocator. DSD (2002)
Jianwen Zhu
Static memory allocation by pointer analysis and coloring. DATE (2001)
Jianwen Zhu, Edward S. Rogers Sr.
Color Permutation: An Iterative Algorithm for Memory Packing. ICCAD (2001)
Jianwen Zhu, Daniel Gajski
Compiling SpecC for simulation. ASP-DAC (2001)
Jianwen Zhu
MetaRTL: raising the abstraction level of RTL design. DATE (2001)
Jianwen Zhu, Daniel Gajski
Soft Scheduling in High Level Synthesis. DAC (1999)
Jianwen Zhu, Daniel Gajski
A unified formal model of ISA and FSMD. CODES (1999)
Jianwen Zhu, Daniel Gajski
OpenJ: An Extensible System Level Design Language. DATE (1999)
Daniel Gajski, Rainer Dömer, Jianwen Zhu
IP-Centric Methodology and Specification Language. DIPES (1998)
Rainer Dömer, Daniel D. Gajski, Jianwen Zhu
Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. 40 (3) (1998)