Farid N. Najm

ORCID

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 25

Top Venues

ICCAD

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ISPD

ISQED

Publications

Cedric Feghali, Farid N. Najm
Fast Current Constraints Generation for Chip Safety. ISQED (2024)
Armen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun-Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stéphane Moreau
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution. ISPD (2023)
Bijan Shahriari, Farid N. Najm
Fast Electromigration Simulation for Chip Power Grids. ISQED (2023)
Valeriy Sukharev, Armen Kteyan, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Jun-Ho Choy, Sofya Torosyan, Yu Zhu
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Adam Issa, Valeriy Sukharev, Farid N. Najm
Electromigration Checking Using a Stochastic Effective Current Model. ICCAD (2020)
Farid N. Najm, Valeriy Sukharev
Efficient Simulation of Electromigration Damage in Large Chip Power Grids Using Accurate Physical Models (Invited Paper). IRPS (2019)
Zahi Moudallal, Valeriy Sukharev, Farid N. Najm
Power Grid Fixing for Electromigration-induced Voltage Failures. ICCAD (2019)
Zahi Moudallal, Farid N. Najm
Power Scheduling With Active RC Power Grids. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm
Power Grid Electromigration Checking Using Physics-Based Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (7) (2018)
Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm
Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems. ICCAD (2017)
Zahi Moudallal, Farid N. Najm
Generating Current Constraints to Guarantee RLC Power Grid Safety. ACM Trans. Design Autom. Electr. Syst. 22 (4) (2017)
Mohammad Fawaz, Farid N. Najm
Power grid verification under transient constraints. ICCAD (2017)
Mohammad Fawaz, Farid N. Najm
Fast Vectorless RLC Grid Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (3) (2017)
Zahi Moudallal, Farid N. Najm
Power scheduling with active power grids. ICCAD (2017)
Mohammad Fawaz, Farid N. Najm
Parallel Simulation-Based Verification of RC Power Grids. ISVLSI (2017)
Mehmet Avci, Farid N. Najm
Verification of the Power and Ground Grids Under General and Hierarchical Constraints. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Abdul-Amir Yassine, Farid N. Najm
A fast layer elimination approach for power grid reduction. ICCAD (2016)
Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm
Fast physics-based electromigration checking for on-die power grids. ICCAD (2016)
Zahi Moudallal, Farid N. Najm
Generating Current Budgets to Guarantee Power Grid Safety. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (11) (2016)
Zahi Moudallal, Farid N. Najm
Generating voltage drop aware current budgets for RC power grids. ISCAS (2016)
Mohammad Fawaz, Farid N. Najm
Accurate verification of RC power grids. DATE (2016)
Mohammad Fawaz, Farid N. Najm
Fast simulation-based verification of RC power grids. CCECE (2016)
Zahi Moudallal, Farid N. Najm
Generating circuit current constraints to guarantee power grid safety. ASP-DAC (2015)
Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm
Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (9) (2015)
Farid N. Najm
Physical Design Challenges in the Chip Power Distribution Network. ISPD (2015)
Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm
Redundancy-aware electromigration checking for mesh power grids. ICCAD (2013)
Mohammad Fawaz, Sandeep Chatterjee, Farid N. Najm
A vectorless framework for power grid electromigration checking. ICCAD (2013)
Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Khaled R. Heloue, Sari Onaissi, Farid N. Najm
Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (4) (2012)
Farid N. Najm
Overview of vectorless/early power grid verification. ICCAD (2012)
Abhishek, Farid N. Najm
Incremental power grid verification. DAC (2012)
Ankit Goyal, Farid N. Najm
Efficient RC power grid verification using node elimination. DATE (2011)
Nahi H. Abdul Ghani, Farid N. Najm
Power grid verification using node and branch dominance. DAC (2011)
Pamela Al Haddad, Farid N. Najm
Power grid correction using sensitivity analysis under an RC model. DAC (2011)
Sari Onaissi, Feroze Taraporevala, Jinfeng Liu, Farid N. Najm
A fast approach for static timing analysis covering all PVT corners. DAC (2011)
Nahi H. Abdul Ghani, Farid N. Najm
Fast Vectorless Power Grid Verification Under an RLC Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Mehmet Avci, Farid N. Najm
Early P/G grid voltage integrity verification. ICCAD (2010)
Meric Aydonat, Farid N. Najm
Power grid correction using sensitivity analysis. ICCAD (2010)
Sean Safarpour, Andreas G. Veneris, Farid N. Najm
Managing verification error traces with bounded model debugging. ASP-DAC (2010)
Imad A. Ferzli, Eli Chiprout, Farid N. Najm
Verification and Codesign of the Package and Die Power Delivery System Using Wavelets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (1) (2010)
Jason Helge Anderson, Farid N. Najm
Low-Power Programmable FPGA Routing Circuitry. IEEE Trans. Very Large Scale Integr. Syst. 17 (8) (2009)
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
Clock skew optimization via wiresizing for timing sign-off covering all process corners. DAC (2009)
Nahi H. Abdul Ghani, Farid N. Najm
Fast vectorless power grid verification using an approximate inverse technique. DAC (2009)
Khaled R. Heloue, Navid Azizi, Farid N. Najm
Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (6) (2009)
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
PSTA-based branch and bound approach to the silicon speedpath isolation problem. ICCAD (2009)
Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm
Quantifying robustness metrics in parameterized static timing analysis. ICCAD (2009)
Sari Onaissi, Farid N. Najm
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Khaled R. Heloue, Sari Onaissi, Farid N. Najm
Efficient block-based parameterized timing analysis covering all potentially critical paths. ICCAD (2008)
Khaled R. Heloue, Farid N. Najm
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (10) (2008)
Khaled R. Heloue, Farid N. Najm
Parameterized timing analysis with general delay models and arbitrary variation sources. DAC (2008)
Farid N. Najm, Noel Menezes, Imad A. Ferzli
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 15 (7) (2007)
Khaled R. Heloue, Navid Azizi, Farid N. Najm
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. DAC (2007)
Imad A. Ferzli, Farid N. Najm, Lars Kruse
Early power grid verification under circuit current uncertainties. ISLPED (2007)
Imad A. Ferzli, Farid N. Najm, Lars Kruse
A geometric approach for early power grid verification using current constraints. ICCAD (2007)
Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE (2007)
Kostas Pagiamtzis, Navid Azizi, Farid N. Najm
A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme. CICC (2006)
Imad A. Ferzli, Farid N. Najm
Analysis and verification of power grids considering process-induced leakage-current variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (1) (2006)
Srinivas Bodapati, Farid N. Najm
High-level current macro model for logic blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Navid Azizi, Farid N. Najm
A family of cells to reduce the soft-error-rate in ternary-CAM. DAC (2006)
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
Voltage-Aware Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Jason Helge Anderson, Farid N. Najm
Active leakage power optimization for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (3) (2006)
Sari Onaissi, Farid N. Najm
A linear-time approach for static timing analysis covering all process corners. ICCAD (2006)
Georges Nabaa, Navid Azizi, Farid N. Najm
An adaptive FPGA architecture with process variation compensation and reduced leakage. DAC (2006)
Nahi H. Abdul Ghani, Farid N. Najm
Handling inductance in early power grid verification. ICCAD (2006)
Bin Wu, Jianwen Zhu, Farid N. Najm
Dynamic-range estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Khaled R. Heloue, Farid N. Najm
Statistical timing analysis with two-sided constraints. ICCAD (2005)
Dionysios Kouroussis, Imad A. Ferzli, Farid N. Najm
Incremental partitioning-based vectorless power grid verification. ICCAD (2005)
Farid N. Najm
On the need for statistical timing analysis. DAC (2005)
Bin Wu, Jianwen Zhu, Farid N. Najm
A non-parametric approach for dynamic range estimation of nonlinear systems. DAC (2005)
Navid Azizi, Farid N. Najm
Look-up table leakage reduction for FPGAs. CICC (2005)
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
Variations-aware low-power design with voltage scaling. DAC (2005)
Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi
A Case for Asymmetric-Cell Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. 13 (7) (2005)
Kavel M. Büyüksahin, Farid N. Najm
Early power estimation for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (7) (2005)
Maha Nizam, Farid N. Najm, Anirudh Devgan
Power grid voltage integrity verification. ISLPED (2005)
David T. Blaauw, Anirudh Devgan, Farid N. Najm
Leakage power: trends, analysis and avoidance. ASP-DAC (2005)
Jason Helge Anderson, Farid N. Najm, Tim Tuan
Active leakage power optimization for FPGAs. FPGA (2004)
Navid Azizi, Farid N. Najm
An Asymmetric SRAM Cell to Lower Gate Leakage. ISQED (2004)
Bin Wu, Jianwen Zhu, Farid N. Najm
Dynamic range estimation for nonlinear systems. ICCAD (2004)
Jason Helge Anderson, Farid N. Najm
Power estimation techniques for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12 (10) (2004)
Bin Wu, Jianwen Zhu, Farid N. Najm
An analytical approach for dynamic range estimation. DAC (2004)
Jason Helge Anderson, Farid N. Najm
A novel low-power FPGA routing switch. CICC (2004)
Farid N. Najm, Noel Menezes
Statistical timing analysis based on a timing yield model. DAC (2004)
Jason Helge Anderson, Farid N. Najm
Interconnect capacitance estimation for FPGAs. ASP-DAC (2004)
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
Worst-case circuit delay taking into account power supply variations. DAC (2004)
Jason Helge Anderson, Farid N. Najm
Low-power programmable routing circuitry for FPGAs. ICCAD (2004)
Subodh Gupta, Farid N. Najm
Energy and peak-current per-cycle estimation at RTL. IEEE Trans. Very Large Scale Integr. Syst. 11 (4) (2003)
Rafik S. Guindi, Farid N. Najm
Design Techniques for Gate-Leakage Reduction in CMOS Circuits. ISQED (2003)
Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. ISLPED (2003)
Imad A. Ferzli, Farid N. Najm
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations. DAC (2003)
Rubil Ahmadi, Farid N. Najm
Timing Analysis in Presence of Power Supply and Ground Voltage Variations. ICCAD (2003)
Dionysios Kouroussis, Farid N. Najm
A static pattern-independent technique for power grid voltage integrity verification. DAC (2003)
Imad A. Ferzli, Farid N. Najm
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations. ICCAD (2003)
Jason Helge Anderson, Farid N. Najm
Switching activity analysis and pre-layout activity prediction for FPGAs. SLIP (2003)
Navid Azizi, Farid N. Najm, Andreas Moshovos
Low-leakage asymmetric-cell SRAM. IEEE Trans. Very Large Scale Integr. Syst. 11 (4) (2003)
Kavel M. Büyüksahin, Farid N. Najm
High-level area estimation. ISLPED (2002)
Jason Helge Anderson, Farid N. Najm
Power-aware technology mapping for LUT-based FPGAs. FPT (2002)
Navid Azizi, Andreas Moshovos, Farid N. Najm
Low-leakage asymmetric-cell SRAM. ISLPED (2002)
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
A multigrid-like technique for power grid analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (10) (2002)
Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
A technique for Improving dual-output domino logic. IEEE Trans. Very Large Scale Integr. Syst. 10 (4) (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Farid N. Najm