Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling.
Navid AziziMuhammad M. KhellahVivek DeFarid N. NajmPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2007)
Keyphrases
- low power
- power consumption
- low power consumption
- single chip
- high speed
- low cost
- vlsi architecture
- logic circuits
- digital signal processing
- vlsi circuits
- cmos technology
- design process
- high power
- power reduction
- mixed signal
- energy dissipation
- motion estimation
- embedded systems
- video coding
- image compression
- real time
- gate array
- ultra low power