Andreas G. Veneris

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 51

Top Venues

BRAINS

IEEE ICBC

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

CoRR

Publications

James Won-Ki Hong, Andreas G. Veneris, Hongtaek Ju, Taeyeol Jeong, Changhoon Kang
Innovations in Blockchain for Crypto Assets and Exchanges. Int. J. Netw. Manag. 34 (4) (2024)
Xun Deng, Sidi Mohamed Beillahi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long
Safeguarding DeFi Smart Contracts against Oracle Deviations. ICSE (2024)
Xun Deng, Sidi Mohamed Beillahi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long
Safeguarding DeFi Smart Contracts against Oracle Deviations. CoRR (2024)
Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris
Deeper: A shared liquidity decentralized exchange design for low trading volume tokens to enhance average liquidity. Int. J. Netw. Manag. 34 (4) (2024)
Jemin Andrew Choi, Sidi Mohamed Beillahi, Srisht Fateh Singh, Panagiotis Michalopoulos, Peilun Li, Andreas G. Veneris, Fan Long
LMPT: A Novel Authenticated Data Structure to Eliminate Storage Bottlenecks for High Performance Blockchains. IEEE Trans. Netw. Serv. Manag. 21 (2) (2024)
Xun Deng, Zihan Zhao, Sidi Mohamed Beillahi, Han Du, Cyrus Minwalla, Keerthi Nelaturu, Andreas G. Veneris, Fan Long
A Robust Front-Running Methodology for Malicious Flash- Loan DeFi Attacks. DAPPS (2023)
Eric Keilty, Keerthi Nelaturu, Anastasia Kastania, Andreas G. Veneris
Gas Optimization Patterns in Move Smart Contracts on the Aptos Blockchain. BRAINS (2023)
Keerthi Nelaturu, Eric Keilty, Andreas G. Veneris
Natural Language-Based Model-Checking Framework for Move Smart Contracts. SDS (2023)
Srisht Fateh Singh, Panagiotis Michalopoulos, Sidi Mohamed Beillahi, Andreas G. Veneris, Fan Long
Möbius: an Atomic State Sharding Design for Account-Based Blockchains. ICBC (2023)
Panagiotis Michalopoulos, Srisht Fateh Singh, Andreas G. Veneris
Inducing Trust in Blockchain-enabled IoT Marketplaces Through Reputation and Dispute Resolution. MetaCom (2023)
Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris
DEEPER: Enhancing Liquidity in Concentrated Liquidity AMM DEX via Sharing. ICBC (2023)
Keerthi Nelaturu, Anastasia Mavridou, Emmanouela Stachtiari, Andreas G. Veneris, Aron Laszka
Correct-by-Design Interacting Smart Contracts and a Systematic Approach for Verifying ERC20 and ERC721 Contracts With VeriSolid. IEEE Trans. Dependable Secur. Comput. 20 (4) (2023)
Zihan Zhao, Sidi Mohamed Beillahi, Ryan Song, Yuxi Cai, Andreas G. Veneris, Fan Long
SigVM: enabling event-driven execution for truly decentralized smart contracts. Proc. ACM Program. Lang. 6 (OOPSLA2) (2022)
Nadia Pocher, Andreas G. Veneris
Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme. IEEE Trans. Netw. Serv. Manag. 19 (2) (2022)
Sidi Mohamed Beillahi, Eric Keilty, Keerthi Nelaturu, Andreas G. Veneris, Fan Long
Automated Auditing of Price Gouging TOD Vulnerabilities in Smart Contracts. ICBC (2022)
Salil S. Kanhere, Andreas G. Veneris, Sachiko Yoshihama, Sandip Chakraborty, Ori Rottenstreich, Marta Beltrán Pardo, Bruno Rodriguez
Guest Editorial: Special Issue on Recent Advances on Blockchain for Network and Service Management. IEEE Trans. Netw. Serv. Manag. 19 (4) (2022)
Jemin Andrew Choi, Sidi Mohamed Beillahi, Peilun Li, Andreas G. Veneris, Fan Long
LMPTs: Eliminating Storage Bottlenecks for Processing Blockchain Transactions. ICBC (2022)
Yuxi Cai, Nafis Irtija, Eirini-Eleni Tsiropoulou, Andreas G. Veneris
Truthful Decentralized Blockchain Oracles. Int. J. Netw. Manag. 32 (2) (2022)
James Meijers, Guntur Dharma Putra, Grammateia Kotsialou, Salil S. Kanhere, Andreas G. Veneris
Cost-Effective Blockchain-based IoT Data Marketplaces with a Credit Invariant. IEEE ICBC (2021)
Nadia Pocher, Andreas G. Veneris
Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme. IEEE ICBC (2021)
Ryan Song, Zihan Zhao, Yuxi Cai, Andreas G. Veneris, Fan Long
SigVM: Toward Fully Autonomous Smart Contracts. CoRR (2021)
James Meijers, Edward Au, Yuxi Cai, Hans-Arno Jacobsen, Shashank Motepalli, Robert Sun, Andreas G. Veneris, Gengrui Zhang, Shiquan Zhang
Blockchain for V2X: A Taxonomy of Design Use Cases and System Requirements. BRAINS (2021)
Keerthi Nelaturu, Sidi Mohamed Beillahit, Fan Long, Andreas G. Veneris
Smart Contracts Refinement for Gas Optimization. BRAINS (2021)
Yuxi Cai, Fan Long, Andreas G. Park, Andreas G. Veneris
Engineering Economics in the Conflux Network. BRAINS (2020)
Neil Veira, Zissis Poulos, Andreas G. Veneris
Searching for Bugs Using Probabilistic Suspect Implications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Keerthi Nelaturu, John Adler, Marco Merlini, Ryan Berryhill, Neil Veira, Zissis Poulos, Andreas G. Veneris
On Public Crowdsource-Based Mechanisms for a Decentralized Blockchain Oracle. IEEE Trans. Engineering Management 67 (4) (2020)
Yuxi Cai, Georgios Fragkos, Eirini-Eleni Tsiropoulou, Andreas G. Veneris
A Truth-Inducing Sybil Resistant Decentralized Blockchain Oracle. BRAINS (2020)
Keerthi Nelaturu, Anastasia Mavridou, Andreas G. Veneris, Aron Laszka
Verified Development and Deployment of Multiple Interacting Smart Contracts with VeriSolid. IEEE ICBC (2020)
Neil Veira, Brian Keng, Kanchana Padmanabhan, Andreas G. Veneris
Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations. IJCAI (2019)
Marco Merlini, Neil Veira, Ryan Berryhill, Andreas G. Veneris
On Public Decentralized Ledger Oracles via a Paired-Question Protocol. IEEE ICBC (2019)
Ryan Berryhill, Andreas G. Veneris
Chasing Minimal Inductive Validity Cores in Hardware Model Checking. FMCAD (2019)
Andreas G. Veneris, Andreas G. Park
Special Drawing Rights in a New Decentralized Century. CoRR (2019)
Neil Veira, Zissis Poulos, Andreas G. Veneris
Suspect2vec: a suspect prediction model for directed RTL debugging. ASP-DAC (2019)
Ryan Berryhill, Alexander Ivrii, Andreas G. Veneris
Finding All Minimal Safe Inductive Sets. SAT (2018)
Neil Veira, Zissis Poulos, Andreas G. Veneris
Suspect set prediction in RTL bug hunting. DATE (2018)
John Adler, Ryan Berryhill, Andreas G. Veneris, Zissis Poulos, Neil Veira, Anastasia Kastania
Astraea: A Decentralized Blockchain Oracle. CoRR (2018)
Ryan Berryhill, Andreas G. Veneris
Efficient suspect selection in unreachable state diagnosis. Ann. Math. Artif. Intell. 82 (4) (2018)
Zissis Poulos, Andreas G. Veneris
Failure Triage in RTL Regression Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (9) (2018)
John Adler, Ryan Berryhill, Andreas G. Veneris, Zissis Poulos, Neil Veira, Anastasia Kastania
Astraea: A Decentralized Blockchain Oracle. iThings/GreenCom/CPSCom/SmartData (2018)
Ryan Berryhill, Andreas G. Veneris
Methodologies for Diagnosis of Unreachable States via Property Directed Reachability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Koushik Pal, Zissis Poulos, Edward Kim, Andreas G. Veneris
Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism. ICDM (2017)
John Adler, Andreas G. Veneris
Leveraging Software Configuration Management in Automated RTL Design Debug. IEEE Des. Test 34 (5) (2017)
John Adler, Ryan Berryhill, Andreas G. Veneris
An extensible perceptron framework for revision RTL debug automation. ASP-DAC (2017)
Ryan Berryhill, Alexander Ivrii, Neil Veira, Andreas G. Veneris
Learning support sets in IC3 and Quip: The good, the bad, and the ugly. FMCAD (2017)
Ryan Berryhill, Neil Veira, Andreas G. Veneris, Zissis Poulos
Learning lemma support graphs in Quip and IC3. IVSW (2017)
Ryan Berryhill, Andreas G. Veneris
Efficient Selection of Suspect Sets in Unreachable State Diagnosis. ISAIM (2016)
Ryan Berryhill, Andreas G. Veneris
A complete approach to unreachable state diagnosability via property directed reachability. ASP-DAC (2016)
Zissis Poulos, Ryan Berryhill, John Adler, Andreas G. Veneris
On simulation-based metrics that characterize the behavior of RTL errors. SummerSim (2016)
Zissis Poulos, Andreas G. Veneris
Exemplar-based Failure Triage for Regression Design Debugging. J. Electron. Test. 32 (2) (2016)
John Adler, Djordje Maksimovic, Andreas G. Veneris
Root-cause analysis for memory-locked errors. DATE (2016)
John Adler, Ryan Berryhill, Andreas G. Veneris
Revision debug with non-linear version history in regression verification. IVSW (2016)
Ryan Berryhill, Andreas G. Veneris
Automated rectification methodologies to functional state-space unreachability. DATE (2015)
Zissis Poulos, Andreas G. Veneris
Mining simulation metrics for failure triage in regression testing. IOLTS (2015)
Djordje Maksimovic, Andreas G. Veneris, Zissis Poulos
Clustering-based revision debug in regression verification. ICCD (2015)
Zissis Poulos, Andreas G. Veneris
Exemplar-based failure triage for regression design debugging. LATS (2015)
Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris
Constructing stability-based clock gating with hierarchical clustering. PATMOS (2015)
Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference (2015)
Brian Keng, Evean Qin, Andreas G. Veneris, Bao Le
Automated debugging of missing assumptions. ASP-DAC (2014)
Hratch Mangassarian, Bao Le, Andreas G. Veneris
Debugging RTL Using Structural Dominance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Zissis Poulos, Andreas G. Veneris
Clustering-based failure triage for RTL regression debugging. ITC (2014)
Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le
Simulation and satisfiability guided counter-example triage for RTL design debugging. ISQED (2014)
Djordje Maksimovic, Bao Le, Andreas G. Veneris
Multiple clock domain synchronization in a QBF-based verification environment. ICCAD (2014)
Brian Keng, Andreas G. Veneris
Path-Directed Abstraction and Refinement for SAT-Based Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (10) (2013)
Bao Le, Dipanjan Sengupta, Andreas G. Veneris
Reviving erroneous stability-based clock-gating using partial Max-SAT. ASP-DAC (2013)
Dipanjan Sengupta, Erhan Ergin, Andreas G. Veneris
Early detection of current hot spots in power gated designs. ISLPED (2013)
Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos
Accelerating post silicon debug of deep electrical faults. IOLTS (2013)
Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris
A failure triage engine based on error trace signature extraction. IOLTS (2013)
Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov
Lazy suspect-set computation: fault diagnosis for deep electrical bugs. ACM Great Lakes Symposium on VLSI (2012)
Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le
Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE (2012)
Brian Keng, Andreas G. Veneris
Path directed abstraction and refinement in SAT-based design debugging. DAC (2012)
Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita
On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC (2012)
Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris
Non-solution implications using reverse domination in a modern SAT-based debugging environment. DATE (2012)
Brian Keng, Andreas G. Veneris
Automated debugging of missing input constraints in a formal verification environment. FMCAD (2012)
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita
Automated data analysis techniques for a modern silicon debug environment. ASP-DAC (2012)
Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov
Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. 2 (2) (2012)
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour
Debugging with dominance: On-the-fly RTL debug solution implications. ICCAD (2011)
Brian Keng, Andreas G. Veneris
Managing complexity in design debugging with sequential abstraction and refinement. ASP-DAC (2011)
Andreas G. Veneris, Brian Keng, Sean Safarpour
From RTL to silicon: The case for automated debug. ASP-DAC (2011)
Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh
Sequence pair based voltage island floorplanning. IGCC (2011)
Elham Safi, Andreas Moshovos, Andreas G. Veneris
Two-Stage, Pipelined Register Renaming. IEEE Trans. Very Large Scale Integr. Syst. 19 (10) (2011)
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton
Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Brian Keng, Sean Safarpour, Andreas G. Veneris
Automated debugging of SystemVerilog assertions. DATE (2011)
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED (2010)
Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris
Automated Design Debugging With Maximum Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Brian Keng, Andreas G. Veneris, Sean Safarpour
An Automated Framework for Correction and Debug of PSL Assertions. MTV (2010)
Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus
Leveraging dominators for preprocessing QBF. DATE (2010)
Brian Keng, Sean Safarpour, Andreas G. Veneris
Bounded Model Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Sean Safarpour, Andreas G. Veneris, Farid N. Najm
Managing verification error traces with bounded model debugging. ASP-DAC (2010)
Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. IEEE Trans. Computers 59 (7) (2010)
Elham Safi, Andreas Moshovos, Andreas G. Veneris
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. IEEE Trans. Very Large Scale Integr. Syst. 18 (3) (2010)
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith
Sequential logic rectifications with approximate SPFDs. DATE (2009)
Sean Safarpour, Andreas G. Veneris
Automated debugging with high level abstraction and refinement. HLDVT (2009)
Elham Safi, Andreas Moshovos, Andreas G. Veneris
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. ICSAMOS (2009)
Andreas G. Veneris, Sean Safarpour
The day Sherlock Holmes decided to do EDA. DAC (2009)
Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
Automated data analysis solutions to silicon debug. DATE (2009)
Sean Safarpour, Andreas G. Veneris
Automated Design Debugging With Abstraction and Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (10) (2009)
Yibin Chen, Sean Safarpour, Andreas G. Veneris, João P. Marques Silva
Spatial and temporal design debug using partial MaxSAT. ACM Great Lakes Symposium on VLSI (2009)
Brian Keng, Andreas G. Veneris
Scaling VLSI design debugging with interpolation. FMCAD (2009)

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Publication Activity (10 Years)

Top Topics

Top Venues

Andreas G. Veneris