Robert K. Brayton

ORCID

Publication Activity (10 Years)

Years Active: 1963-2022
Publications (10 Years): 25

Top Venues

DAC

DATE

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ASP-DAC

Publications

Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton
Deep Integration of Circuit Simulator and SAT Solver. DAC (2021)
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
Simulation-Guided Boolean Resubstitution. CoRR (2020)
Yu-Yun Dai, Robert K. Brayton
Verification and Synthesis of Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (2) (2019)
Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton
SAT-based area recovery in structural technology mapping. ASP-DAC (2018)
Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli
Practical exact synthesis. DATE (2018)
Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
Improvements to boolean resynthesis. DATE (2018)
Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton
Efficient computation of ECO patch functions. DAC (2018)
Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic
Canonical computation without canonical representation. DAC (2018)
Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton
Property directed reachability with word-level abstraction. FMCAD (2017)
Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis
Fast-extract with cube hashing. ASP-DAC (2017)
Yu-Yun Dai, Robert K. Brayton
Circuit recognition with deep learning. HOST (2017)
Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
Enabling exact delay synthesis. ICCAD (2017)
Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton
2QBF: Challenges and Solutions. SAT (2016)
Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT (2016)
Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD (2016)
Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton
Efficient uninterpreted function abstraction and refinement for word-level model checking. FMCAD (2016)
Hamid Savoj, Alan Mishchenko, Robert K. Brayton
m-Inductive Property of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (6) (2016)
Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene
Technology Mapping into General Programmable Cells. FPGA (2015)
Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
Bi-Decomposition Using Boolean Relations. DSD (2015)
Robert K. Brayton, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa
Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue]. Proc. IEEE 103 (11) (2015)
Tiziano Villa, Alexandre Petrenko, Nina Yevtushenko, Alan Mishchenko, Robert K. Brayton
Component-Based Design by Solving Language Equations. Proc. IEEE 103 (11) (2015)
Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko
Automated Synthesis of Protocol Converters with BALM-II. SEFM Workshops (2015)
Yu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton
Sequential equivalence checking of clock-gated circuits. DAC (2015)
Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
Reverse Engineering with Simulation Graphs. FMCAD (2015)
Hamid Savoj, Alan Mishchenko, Robert K. Brayton
Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (2) (2014)
Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB (2014)
Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC (2014)
Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla
GLA: gate-level abstraction revisited. DATE (2013)
Jiang Long, Robert K. Brayton, Michael L. Case
LEC: Learning Driven Data-path Equivalence Checking. DIFTS@FMCAD (2013)
Sayak Ray, Robert K. Brayton
Ranking structure in communication fabrics. MEMOCODE (2013)
Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma
A semi-canonical form for sequential AIGs. DATE (2013)
Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen
Mapping into LUT structures. DATE (2012)
Sayak Ray, Robert K. Brayton
Scalable progress verification in credit-based flow-control systems. DATE (2012)
Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets
Delay optimization using SOP balancing. ICCAD (2011)
Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD (2011)
Niklas Eén, Alan Mishchenko, Robert K. Brayton
Efficient implementation of property directed reachability. FMCAD (2011)
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton
Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang
Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Robert K. Brayton, Alan Mishchenko
ABC: An Academic Industrial-Strength Verification Tool. CAV (2010)
Robert K. Brayton, Jason Cong
NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Des. Test Comput. 27 (3) (2010)
Alan Mishchenko, Robert K. Brayton, Stephen Jang
Global delay optimization using structural choices. FPGA (2010)
Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton
Combinational techniques for sequential equivalence checking. FMCAD (2010)
Robert K. Brayton, Jason Cong
NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Des. Test Comput. 27 (2) (2010)
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith
Sequential logic rectifications with approximate SPFDs. DATE (2009)
Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton
SmartOpt: an industrial strength framework for logic synthesis. FPGA (2009)
Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang
Scalable don't-care-based logic optimization and resynthesis. FPGA (2009)
Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton
Speculative reduction-based scalable redundancy identification. DATE (2009)
Fan Mo, Robert K. Brayton
Placement based multiplier rewiring for cell-based designs. ICCAD (2008)
Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony
Invariant-Strengthened Elimination of Dependent State Elements. FMCAD (2008)
Alan Mishchenko, Robert K. Brayton
Recording Synthesis History for Sequential Verification. FMCAD (2008)
Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee
Boolean factoring and decomposition of logic networks. ICCAD (2008)
Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton
Merging nodes under sequential observability. DAC (2008)
Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
Compositionally Progressive Solutions of Synchronous FSM Equations. Discret. Event Dyn. Syst. 18 (1) (2008)
Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang
Scalable and scalably-verifiable sequential synthesis. ICCAD (2008)
Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton
Scalable min-register retiming under timing and initializability constraints. DAC (2008)
Alan Mishchenko, Robert K. Brayton
SAT-Based Complete Don't-Care Computation for Network Optimization CoRR (2007)
Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton
Combinational and sequential mapping with priority cuts. ICCAD (2007)
Fan Mo, Robert K. Brayton
A simultaneous bus orientation and bused pin flipping algorithm. ICCAD (2007)
Michael L. Case, Alan Mishchenko, Robert K. Brayton
Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD (2007)
Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton
Automating Logic Rectification by Approximate SPFDs. ASP-DAC (2007)
Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann
On Resolution Proofs for Combinational Equivalence. DAC (2007)
Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
Efficient Solution of Language Equations Using Partitioned Representations CoRR (2007)
Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
A new algorithm for the largest compositionally progressive solution of synchronous language equations. ACM Great Lakes Symposium on VLSI (2007)
Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton
Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD (2007)
Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (2) (2007)
Fan Mo, Robert K. Brayton
Semi-detailed bus routing with variation reduction. ISPD (2007)
Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC (2006)
Alan Mishchenko, Robert K. Brayton
A theory of nondeterministic networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén
Improvements to combinational equivalence checking. ICCAD (2006)
Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton
Factor cuts. ICCAD (2006)
Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
Improvements to technology mapping for LUT-based FPGAs. FPGA (2006)
Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
Reducing Structural Bias in Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC (2006)
Jie-Hong Roland Jiang, Robert K. Brayton
Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
Reducing structural bias in technology mapping. ICCAD (2005)
Yinghua Li, Alex Kondratyev, Robert K. Brayton
Synthesis methodology for built-in at-speed testing. ICCAD (2005)
Yinghua Li, Alex Kondratyev, Robert K. Brayton
Gaining Predictability and Noise Immunity in Global Interconnects. ACSD (2005)
Alan Mishchenko, Robert K. Brayton
SAT-Based Complete Don't-Care Computation for Network Optimization. DATE (2005)
Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
Efficient Solution of Language Equations Using Partitioned Representations. DATE (2005)
Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (7) (2004)
Fan Mo, Robert K. Brayton
A timing-driven module-based chip design flow. DAC (2004)
Satrajit Chatterjee, Robert K. Brayton
A new incremental placement algorithm and its application to congestion-aware divisor extraction. ICCAD (2004)
Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
On breakable cyclic definitions. ICCAD (2004)
Jie-Hong Roland Jiang, Robert K. Brayton
Functional Dependency for Verification Reduction. CAV (2004)
Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
Reducing Multi-Valued Algebraic Operations to Binary. DATE (2003)
Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8 (2) (2003)
Yunjian Jiang, Slobodan Matic, Robert K. Brayton
Generalized cofactoring for logic function evaluation. DAC (2003)
Fan Mo, Robert K. Brayton
Fishbone: a block-level placement and routing scheme. ISPD (2003)
Alan Mishchenko, Robert K. Brayton
A Theory of Non-Deterministic Networks. ICCAD (2003)
Jie-Hong Roland Jiang, Robert K. Brayton
On the verification of sequential equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Fan Mo, Robert K. Brayton
PLA-based regular structures and their synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. DATE (2003)
Yunjian Jiang, Robert K. Brayton
Don't cares in logic minimization of extended finite state machines. ASP-DAC (2003)
Fan Mo, Robert K. Brayton
River PLAs: a regular circuit structure. DAC (2002)
Alan Mishchenko, Robert K. Brayton
Simplification of non-deterministic multi-valued networks. ICCAD (2002)
Alan Mishchenko, Robert K. Brayton
Simplification of Non-Deterministic Multi-Valued Networks. IWLS (2002)
Yunjian Jiang, Robert K. Brayton
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. IWLS (2002)
Fan Mo, Robert K. Brayton
Whirlpool PLAs: a regular logic structure and their synthesis. ICCAD (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Robert K. Brayton