Luca G. Amarù

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 22

Top Topics

Optimization Problems

Canonical Representation

Top Venues

Publications

Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
Scalable Sequential Optimization Under Observability Don't Cares. DATE (2024)
Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
Scalable Sequential Optimization Under Observability Don't Cares. CoRR (2023)
Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
Improving LUT-based optimization for ASICs. DAC (2022)
Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
Majority-based Design Flow for AQFP Superconducting Family. DATE (2022)
Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC (2021)
Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC (2021)
He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton
Deep Integration of Circuit Simulator and SAT Solver. DAC (2021)
Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. IACR Cryptol. ePrint Arch. 2020 (2020)
Max Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon
A Scalable Mixed Synthesis Framework for Heterogeneous Networks. DATE (2020)
Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8 (2020)
Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. DATE (2020)
Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
SAT-Sweeping Enhanced for Logic Synthesis. DAC (2020)
Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Scalable Boolean Methods in a Modern Synthesis Flow. DATE (2019)
Walter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. ICCAD (2019)
Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. ISVLSI (2019)
Eleonora Testa, Mathias Soeken, Luca G. Amarù, Giovanni De Micheli
Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications. DAC (2019)
Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
Logic Optimization of Majority-Inverter Graphs. MBMV (2019)
Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC (2019)
Debjyoti Bhattacharjee, Luca G. Amarù, Anupam Chattopadhyay
Technology-aware logic synthesis for ReRAM based in-memory computing. DATE (2018)
Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli
Size Optimization of MIGs with an Application to QCA and STMG Technologies. NANOARCH (2018)
Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken
Majority logic synthesis. ICCAD (2018)
Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic
Canonical computation without canonical representation. DAC (2018)