Matheus Trevisan Moreira

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 15

Top Venues

ASYNC

SBCCI

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Pontifícia Universidade Católica do Rio Grande do Sul, Brazil (PHD)

Education History

Pontifícia Universidade Católica do Rio Grande do Sul, Brazil

PHD

Publications

Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC (2024)
Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. SBCCI (2023)
Matheus Trevisan Moreira, William Koven, Tony F. Wu, H. Ekin Sumbul, Edith Beigné
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC (2023)
Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC (2021)
Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Alexandre F. Hampel, Fernando Gehm Moraes
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (11) (2021)
Leonardo Rezende Juracy, Matheus Trevisan Moreira, Alexandre de Morais Amory, Fernando Gehm Moraes
A Survey of Aging Monitors and Reconfiguration Techniques. CoRR (2020)
Matheus Trevisan Moreira, Stefano Giaconi
Chronos Link: A QDI Interconnect for Modern SoCs. ASYNC (2020)
Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory
Optimized Design of an LSSD Scan Cell. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans
A standard cell characterization flow for non-standard voltage supplies. SBCCI (2016)
Felipe Todeschini Bortolon, Sergio Johann Filho, Matheus Gibiluka, Sergio Bampi, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel, Matheus Trevisan Moreira
Design and analysis of the HF-RISC processor targeting voltage scaling applications. SBCCI (2016)
Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC (2015)
Matheus Trevisan Moreira, Michel Evandro Arendt, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Static Differential NCL Gates: Toward Low Power. IEEE Trans. Circuits Syst. II Express Briefs (6) (2015)
Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. DSD (2015)
Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Blade - A Timing Violation Resilient Asynchronous Template. ASYNC (2015)
Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
BAT-Hermes: A transition-signaling bundled-data NoC router. LASCAS (2015)
Matheus Trevisan Moreira, Michel Evandro Arendt, Ricardo Aquino Guazzelli, Ney Laert Vilar Calazans
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design. ASYNC (2014)
Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Beware the Dynamic C-Element. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. ACM Great Lakes Symposium on VLSI (2014)
Matheus Trevisan Moreira, Guilherme Trojan, Fernando Gehm Moraes, Ney Laert Vilar Calazans
Spatially Distributed Dual-Spacer Null Convention Logic Design. J. Low Power Electron. 10 (3) (2014)
Matheus Trevisan Moreira, Ney Laert Vilar Calazans
Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow. ISVLSI (2013)
Matheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. DSD (2013)
Matheus Trevisan Moreira, Ney Laert Vilar Calazans
Voltage scaling on C-elements: A speed, power and energy efficiency analysis. ICCD (2013)

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Publication Activity (10 Years)

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Matheus Trevisan Moreira