Melvin A. Breuer

Publication Activity (10 Years)

Years Active: 1962-2016
Publications (10 Years): 1

Top Venues

ASYNC

DATE

ISQED

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Shuo Wang, Yue Gao, Melvin A. Breuer
GlYFF: A framework for global yield and floorplan aware design optimization. ISQED (2015)
Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC (2015)
Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Design and Analysis of Testable Mutual Exclusion Elements. ASYNC (2015)
Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel
Blade - A Timing Violation Resilient Asynchronous Template. ASYNC (2015)
Yue Gao, Melvin A. Breuer, Yanzhi Wang
A new paradigm for trading off yield, area and performance to enhance performance per wafer. DATE (2013)
Yue Gao, Sandeep K. Gupta, Melvin A. Breuer
Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. DATE (2013)
Yue Gao, Yang Zhang, Da Cheng, Melvin A. Breuer
Trading off area, yield and performance via hybrid redundancy in multi-core architectures. VTS (2013)
Zhaoliang Pan, Melvin A. Breuer
Error Rate Estimation for Defective Circuits via Ones Counting. ACM Trans. Design Autom. Electr. Syst. 17 (1) (2012)
Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian
Theory of redundancy for logic circuits to maximize yield/area. ISQED (2012)
Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
A design flow to maximize yield/area of physical devices via redundancy. ITC (2012)
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (5) (2012)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (6) (2011)
Melvin A. Breuer
Hardware that produces bounded rather than exact results. DAC (2010)
Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. Asian Test Symposium (2010)
Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. DATE (2010)
Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee
Tolerance of performance degrading faults for effective yield improvement. ITC (2009)
Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. Asian Test Symposium (2009)
Zhaoliang Pan, Melvin A. Breuer
Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER). VTS (2008)
Melvin A. Breuer
Clarifying the record on testability cost functions. IEEE Des. Test Comput. 25 (6) (2008)
Melvin A. Breuer, Haiyang (Henry) Zhu
An Illustrated Methodology for Analysis of Error Tolerance. IEEE Des. Test Comput. 25 (2) (2008)
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. ATS (2008)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Trans. Reliab. 57 (1) (2008)
Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults. ATS (2007)
Zhaoliang Pan, Melvin A. Breuer
Estimating Error Rate in Defective Logic Using Signature Analysis. IEEE Trans. Computers 56 (5) (2007)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE (2007)
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS (2006)
Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
Diagnosis of delay faults due to resistive bridges, delay variations and defects. ATS (2006)
Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
STAX: statistical crosstalk target set compaction. DATE Designers' Forum (2006)
Melvin A. Breuer, Haiyang (Henry) Zhu
Error-Tolerance and Multi-Media. IIH-MSP (2006)
Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
Test Generation for Weak Resistive Bridges. ATS (2006)
Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
Multiple tests for each gate delay fault: higher coverage and lower test application cost. ITC (2005)
Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
A novel test methodology based on error-rate to support error-tolerance. ITC (2005)
Melvin A. Breuer
Multi-media Applications and Imprecise Computation. DSD (2005)
Melvin A. Breuer
Let's Think Analog. ISVLSI (2005)
Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium (2004)
Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian
Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium (2004)
Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Des. Test Comput. 21 (3) (2004)
Melvin A. Breuer
Intelligible Test Techniques to Support Error-Tolerance. Asian Test Symposium (2004)
Melvin A. Breuer
Determining error rate in error tolerant VLSI chips. DELTA (2004)
Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC (2004)
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium (2003)
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS (2003)
Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS (2003)
I-De Huang, Sandeep K. Gupta, Melvin A. Breuer
Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD (2002)
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (10) (2002)
Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
XIDEN: Crosstalk Target Identification Framework. ITC (2002)
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electron. Test. 18 (1) (2002)
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electron. Test. 18 (1) (2002)
Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
Crosstalk test generation on pseudo industrial circuits: a case study. ITC (2001)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6 (3) (2001)
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS (2001)
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC (2001)
Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
Switch-level delay test of domino logic circuits. ITC (2001)
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium (2000)
Melvin A. Breuer, Sandeep K. Gupta
New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design (2000)
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers 49 (11) (2000)
Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi
Fundamental CAD algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (12) (2000)
Melvin A. Breuer, Kwang-Ting Cheng
Challenges for the Academic Test Community. Asian Test Symposium (2000)
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium (2000)
Melvin A. Breuer
High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. VTS (2000)
Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
Switch-level delay test. ITC (1999)
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
Test generation for crosstalk-induced delay in integrated circuits. ITC (1999)
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD (1999)
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
Test Generation for Ground Bounce in Internal Logic Circuitry. VTS (1999)
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
Test generation in VLSI circuits for crosstalk noise. ITC (1998)
Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta
Process Variations and their Impact on Circuit Operation. DFT (1998)
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
Bounds on pseudoexhaustive test lengths. IEEE Trans. Very Large Scale Integr. Syst. 6 (3) (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Estimation of BIST Resources During High-Level Synthesis. J. Electron. Test. 13 (3) (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electron. Test. 13 (2) (1998)
Debaditya Mukherjee, Melvin A. Breuer
An IEEE 1149.1 Compliant Test Control Architecture. J. Electron. Test. 13 (3) (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Scheduling and Module Assignment for Reducing Bist Resources. DATE (1998)
Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC (1997)
Melvin A. Breuer, Bozena Kaminska, J. McDermid, V. Rayapathi, Donald L. Wheater
Will 0.1um Digital Circuits Require Mixed-Signal Testing. VTS (1997)
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
High Quality Robust Tests for Path Delay Faults. VTS (1997)
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS (1997)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC (1996)
Melvin A. Breuer, Sandeep K. Gupta
Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC (1996)
Sridhar Narayanan, Melvin A. Breuer
Asynchronous multiple scan chain. VTS (1995)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC (1995)
Rajesh Gupta, Melvin A. Breuer
Partial scan design of register-transfer level circuits. J. Electron. Test. 7 (1-2) (1995)
Sridhar Narayanan, Melvin A. Breuer
Reconfiguration techniques for a single scan chain. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (6) (1995)
Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
Test embedding with discrete logarithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (5) (1995)
Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer
An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (12) (1995)
Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC (1994)
Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
Test embedding with discrete logarithms. VTS (1994)
Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
Control Strategies for Chip-Based DFT/BIST Hardware. ITC (1994)
Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (5) (1994)
Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC (1994)
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC (1993)
Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
Optimal Configuring of Multiple Scan Chains. IEEE Trans. Computers 42 (9) (1993)
Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
Merging multiple FSM controllers for DFT/BIST hardware. ICCAD (1993)
Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
Generating a family of testable designs using the BILBO methodology. J. Electron. Test. 4 (1) (1993)
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC (1993)
Jung-Cheun Lien, Melvin A. Breuer
Test program synthesis for modules and chips having boundary scan. J. Electron. Test. 4 (2) (1993)
Sridhar Narayanan, Melvin A. Breuer
Reconfigurable scan chains: a novel approach to reduce test application time. ICCAD (1993)
Rajesh Gupta, Melvin A. Breuer
Testability properties of acyclic structures and applications to partial scan design. VTS (1992)
Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
Minimal area merger of finite state machine controllers. EURO-DAC (1992)
Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
Optimal Sequencing of Scan Registers. ITC (1992)

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Publication Activity (10 Years)

Top Topics

Top Venues

Melvin A. Breuer