Ishwar Parulkar

Publication Activity (10 Years)

Years Active: 1994-2010
Publications (10 Years): 0

Publications

Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota
Panel: Reliability of data centers: Hardware vs. software. DATE (2010)
Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar
Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. ETS (2009)
Ishwar Parulkar, Babu Turumella
Comprehensive Approach to High-Performance Server Chipset Debug. IEEE Des. Test Comput. 26 (3) (2009)
Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar
Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. IEEE J. Solid State Circuits 44 (1) (2009)
Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar
Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor. ITC (2008)
Cristian Constantinescu, Ishwar Parulkar, R. Harper, Sarah Michalak
Silent Data Corruption - Myth or reality? DSN (2008)
Georgios K. Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar
Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor. ISSCC (2008)
Ishwar Parulkar, Robert Cypher
Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. IOLTS (2005)
Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski
Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. ITC (2005)
Ishwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar
Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field. ITC (2005)
Peter Dahlgren, Paul Dickinson, Ishwar Parulkar
Latch Divergency In Microprocessor Failure Analysis. ITC (2003)
Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar
Chip Multi-Processors. ITC (2002)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6 (3) (2001)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Estimation of BIST Resources During High-Level Synthesis. J. Electron. Test. 13 (3) (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electron. Test. 13 (2) (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Scheduling and Module Assignment for Reducing Bist Resources. DATE (1998)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC (1996)
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC (1995)
Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC (1994)