Thomas A. Ziaja

Publication Activity (10 Years)

Years Active: 1994-2012
Publications (10 Years): 0

Top Topics

Programmable Logic

Top Venues

Publications

Manish Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja
Sparc T4: A Dynamically Threaded Server-on-a-Chip. IEEE Micro 32 (2) (2012)
Thomas A. Ziaja, Poh J. Tan
Efficient Array Characterization in the UltraSPARC T2. VTS (2009)
Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen
Transition Test on UltraSPARC- T2 Microprocessor. ITC (2008)
Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh
Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. ITC (2007)
Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar
Chip Multi-Processors. ITC (2002)
Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD (2001)
Thomas A. Ziaja
Using LSSD to test modules at the board level. ITC (1999)
Thomas A. Ziaja, Earl E. Swartzlander Jr.
Comprehensive Modeling of VLSI Test. DFT (1996)
Thomas A. Ziaja, Earl E. Swartzlander Jr.
Characterization and analysis of errors in circuit test. DFT (1995)
Thomas A. Ziaja, Earl E. Swartzlander Jr.
Boundary scan in board manufacturing. J. Electron. Test. 5 (2-3) (1994)