Earl E. Swartzlander Jr.

ORCID

Publication Activity (10 Years)

Years Active: 1973-2022
Publications (10 Years): 26

Top Venues

ACSSC

IEEE Trans. Computers

MWSCAS

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Pragnesh Patel, Aman Arora, Earl E. Swartzlander Jr., Lizy K. John
LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning. ISQED (2022)
Stafford Hutchins, Earl E. Swartzlander Jr.
A Bfloat16 Fused Multiplier-Adder. UEMCON (2020)
Trenton J. Grale, Earl E. Swartzlander Jr.
) Modular Squarers. MWSCAS (2019)
Alexander J. Groszewski, Earl E. Swartzlander Jr.
A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing. ACSSC (2019)
Weiqiang Liu, Tian Cao, Peipei Yin, Yuying Zhu, Chenghua Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi
Design and Analysis of Approximate Redundant Binary Multipliers. IEEE Trans. Computers 68 (6) (2019)
Weiqiang Liu, Faqiang Mei, Chenghua Wang, Máire O'Neill, Earl E. Swartzlander Jr.
Data Compression Device Based on Modified LZ4 Algorithm. IEEE Trans. Consumer Electron. 64 (1) (2018)
Nagaraja Revanna, Earl E. Swartzlander Jr.
Memristor Adder Design. MWSCAS (2018)
Lizy K. John, Earl E. Swartzlander Jr.
Memristor-Based Computing. IEEE Micro 38 (5) (2018)
Peipei Yin, Chenghua Wang, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications. J. Signal Process. Syst. 90 (4) (2018)
Xiao-Ping Cui, Weiqiang Liu, Shumin Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. J. Signal Process. Syst. 90 (3) (2018)
Trenton J. Grale, Earl E. Swartzlander Jr.
) multipliers. ACSSC (2017)
Lauren Guckert, Earl E. Swartzlander Jr.
MAD Gates - Memristor Logic Design Using Driver Circuitry. IEEE Trans. Circuits Syst. II Express Briefs (2) (2017)
Lauren Guckert, Earl E. Swartzlander Jr.
Optimized Memristor-Based Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Lauren Guckert, Earl E. Swartzlander Jr.
Dadda Multiplier designs using memristors. ICICDT (2017)
Weiqiang Liu, Earl E. Swartzlander Jr., Máire O'Neill
Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing. IEEE Trans. Emerg. Top. Comput. 5 (2) (2017)
Nagaraja Revanna, Lauren Guckert, Earl E. Swartzlander Jr.
The future of computing - Arithmetic circuits implemented with memristors. ACSSC (2017)
Xiao-Ping Cui, Wenwen Dong, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes. IEEE Trans. Computers 66 (12) (2017)
Lauren Guckert, Earl E. Swartzlander Jr.
Optimized memristor-based ripple carry adders. ACSSC (2016)
Xiao-Ping Cui, Weiqiang Liu, Chen Xin, Earl E. Swartzlander Jr., Fabrizio Lombardi
A Modified Partial Product Generator for Redundant Binary Multipliers. IEEE Trans. Computers 65 (4) (2016)
Nagaraja Revanna, Earl E. Swartzlander Jr.
Memristor based adder circuit design. ACSSC (2016)
Jongwook Sohn, Earl E. Swartzlander Jr.
A Fused Floating-Point Four-Term Dot Product Unit. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2016)
Nagaraja Revanna, Earl E. Swartzlander Jr.
Arithmetic circuit design with memristor based high fan-out logic gates. UEMCON (2016)
Robert J. Ascott, Earl E. Swartzlander Jr.
Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow). ACSSC (2015)
Weiqiang Liu, Earl E. Swartzlander Jr.
Design of 3-D quantum-dot cellular automata adders. IEICE Electron. Express 12 (6) (2015)
Mike O'Connor, Earl E. Swartzlander Jr.
Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication. ACSSC (2015)
Michael B. Sullivan, Earl E. Swartzlander Jr.
Low-Cost Duplicate Multiplication. ARITH (2015)
Jongwook Sohn, Earl E. Swartzlander Jr.
A Fused Floating-Point Three-Term Adder. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2014)
Kihwan Jun, Earl E. Swartzlander Jr.
Improved non-restoring square root algorithm with dual path calculation. ACSSC (2014)
Inwook Kong, Seong-Wan Kim, Earl E. Swartzlander Jr.
Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata. IEEE Trans. Computers 63 (10) (2014)
Divya Mahajan, Matheen Musaddiq, Earl E. Swartzlander Jr.
Memristor based adders. ACSSC (2014)
Kihwan Jun, Earl E. Swartzlander Jr.
Improved non-restoring division algorithm with dual path calculation. MWSCAS (2013)
Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.
QCA Systolic Array Design. IEEE Trans. Computers 62 (3) (2013)
Hani H. Saleh, Baker S. Mohammad, Earl E. Swartzlander Jr.
The optimum Booth radix for low power integer multipliers. IDT (2013)
Jae Hong Min, Earl E. Swartzlander Jr.
Fused floating-point magnitude unit. MWSCAS (2013)
Jae Hong Min, Earl E. Swartzlander Jr.
Fused floating-point two-term sum-of-squares unit. ASAP (2013)
Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr.
Implementation of a high speed multiplier using carry lookahead adders. ACSSC (2013)
Jongwook Sohn, Earl E. Swartzlander Jr.
Improved Architectures for a Floating-Point Fused Dot Product Unit. IEEE Symposium on Computer Arithmetic (2013)
Earl E. Swartzlander Jr.
STARS: Electronic Calculators: Desktop to Pocket. Proc. IEEE 101 (12) (2013)
Michael B. Sullivan, Earl E. Swartzlander Jr.
On separable error detection for addition. ACSSC (2013)
Michael B. Sullivan, Earl E. Swartzlander Jr.
Truncated Logarithmic Approximation. IEEE Symposium on Computer Arithmetic (2013)
Weiqiang Liu, Saket Srivastava, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
Power analysis attack of QCA circuits: A case study of the Serpent cipher. ISCAS (2013)
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (2) (2013)
Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
Cost-efficient decimal adder design in Quantum-dot cellular automata. ISCAS (2012)
Hyesook Lim, Soohyun Lee, Earl E. Swartzlander Jr.
A new hierarchical packet classification algorithm. Comput. Networks 56 (13) (2012)
Kihwan Jun, Earl E. Swartzlander Jr.
Modified non-restoring division algorithm with improved delay profile and error correction. ACSCC (2012)
Jongwook Sohn, Earl E. Swartzlander Jr.
Improved Architectures for a Fused Floating-Point Add-Subtract Unit. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2012)
Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.
A review of QCA adders and metrics. ACSCC (2012)
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
Keep it straight: teaching placement how to better handle designs with datapaths. ISPD (2012)
Michael B. Sullivan, Earl E. Swartzlander Jr.
Long Residue Checking for Adders. ASAP (2012)
Jae Hong Min, Jongwook Sohn, Earl E. Swartzlander Jr.
A low-power dual-path floating-point fused add-subtract unit. ACSCC (2012)
Michael B. Sullivan, Earl E. Swartzlander Jr.
Truncated error correction for flexible approximate multiplication. ACSCC (2012)
Earl E. Swartzlander Jr., Hani H. Saleh
FFT Implementation with Fused Floating-Point Operations. IEEE Trans. Computers 61 (2) (2012)
Sreenivaas Muthyala Sudhakar, Kumar P. Chidambaram, Earl E. Swartzlander Jr.
Hybrid Han-Carlson adder. MWSCAS (2012)
Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.
Quantifying academic placer performance on custom designs. ISPD (2011)
Andrew G. Shafer, Lyndsi R. Parker, Earl E. Swartzlander Jr.
The fully-serial pipelined multiplier. ACSCC (2011)
Inwook Kong, Earl E. Swartzlander Jr.
A Goldschmidt Division Method With Faster Than Quadratic Convergence. IEEE Trans. Very Large Scale Integr. Syst. 19 (4) (2011)
Michael B. Sullivan, Earl E. Swartzlander Jr.
Hybrid residue generators for increased efficiency. ACSCC (2011)
Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
Design rules for Quantum-dot Cellular Automata. ISCAS (2011)
Jae Hong Min, Seong-Wan Kim, Earl E. Swartzlander Jr.
A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers. ACSCC (2011)
Waqas Akram, Earl E. Swartzlander Jr.
Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters. J. Signal Process. Syst. 65 (2) (2011)
Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.
QCA Systolic Matrix Multiplier. ISVLSI (2010)
Terence K. Rodrigues, Earl E. Swartzlander Jr.
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. IEEE Trans. Computers 59 (4) (2010)
Ron S. Waters, Earl E. Swartzlander Jr.
A Reduced Complexity Wallace Multiplier Reduction. IEEE Trans. Computers 59 (8) (2010)
Inwook Kong, Earl E. Swartzlander Jr.
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division. IEEE Trans. Computers 59 (12) (2010)
Waqas Akram, Earl E. Swartzlander Jr.
A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. ICASSP (2010)
Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.
Priority Tries for IP Address Lookup. IEEE Trans. Computers 59 (6) (2010)
Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham
High speed recursion-free CORDIC architecture. SoCC (2010)
Heumpil Cho, Earl E. Swartzlander Jr.
Adder and Multiplier Design in Quantum-Dot Cellular Automata. IEEE Trans. Computers 58 (6) (2009)
Inwook Kong, Earl E. Swartzlander Jr., Seong-Wan Kim
Design of a Goldschmidt iterative divider for quantum-dot cellular automata. NANOARCH (2009)
Robert J. Ascott, Earl E. Swartzlander Jr.
JavaFlow - A Java dataflow machine. SoCC (2009)
Bassam Jamil Mohd, Earl E. Swartzlander Jr.
A Power-Scalable Switch-Based Multi-processor FFT. ASAP (2009)
Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
ASIC evaluation of ECHO hash function. SoCC (2009)
Hani H. Saleh, Earl E. Swartzlander Jr.
A floating-point fused dot-product unit. ICCD (2008)
Robert T. Grisamore, Earl E. Swartzlander Jr.
Negative Save Sign Extension for Multi-term Adders and Multipliers. J. Signal Process. Syst. 52 (1) (2008)
Inwook Kong, Earl E. Swartzlander Jr.
A rounding method with improved error tolerance for division by convergence. ACSCC (2008)
Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds
Bridge Floating-Point Fused Multiply-Add Design. IEEE Trans. Very Large Scale Integr. Syst. 16 (12) (2008)
Vijay K. Jain, Earl E. Swartzlander Jr.
32 bit single cycle nonlinear VLSI cell for the ICA algorithm. ICASSP (2008)
Earl E. Swartzlander Jr., Hani H. Saleh
Fused floating-point arithmetic for DSP. ACSCC (2008)
Earl E. Swartzlander Jr.
Systolic FFT Processors: A Personal Perspective. J. Signal Process. Syst. 53 (1-2) (2008)
Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.
High performance IP lookup circuit using DDR SDRAM. SoCC (2008)
Youngmoon Choi, Earl E. Swartzlander Jr.
Speculative Carry Generation With Prefix Adder. IEEE Trans. Very Large Scale Integr. Syst. 16 (3) (2008)
Hani H. Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ICCD (2007)
Heumpil Cho, Earl E. Swartzlander Jr.
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. IEEE Symposium on Computer Arithmetic (2007)
Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. VLSI-SoC (2007)
Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. VLSI-SoC (Selected Papers) (2007)
Earl E. Swartzlander Jr.
The Negative Two's Complement Number System. J. VLSI Signal Process. 49 (1) (2007)
Chang Yong Kang, Earl E. Swartzlander Jr.
Digit-pipelined direct digital frequency synthesis based on differential CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2006)
Tung N. Pham, Earl E. Swartzlander Jr.
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. ASAP (2006)
Earl E. Swartzlander Jr.
Systolic FFT Processors: Past, Present and Future. ASAP (2006)
Moboluwaji O. Sanu, Earl E. Swartzlander Jr.
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. ASAP (2005)
Earl E. Swartzlander Jr.
Three Dimensional System on Chip Technology, invited. IWSOC (2005)
Youngmoon Choi, Earl E. Swartzlander Jr.
Parallel Prefix Adder Design with Matrix Representation. IEEE Symposium on Computer Arithmetic (2005)
Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase
Parallel Montgomery Multipliers. ASAP (2004)
Earl E. Swartzlander Jr.
A Review of Large Parallel Counter Designs. ISVLSI (2004)
Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.
A self-testing method for the pipelined A/D converter. ISCAS (1) (2003)
Mohammad Ibrahim, Earl E. Swartzlander Jr.
Guest Editorial. J. VLSI Signal Process. 33 (1-2) (2003)
Ayman M. El-Khashab, Earl E. Swartzlander Jr.
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. ASAP (2003)
Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.
Quadruple Time Redundancy Adders. DFT (2003)
Chang Yong Kang, Earl E. Swartzlander Jr.
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. ASAP (2002)
Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. J. VLSI Signal Process. 31 (2) (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Earl E. Swartzlander Jr.