John V. McCanny

Publication Activity (10 Years)

Years Active: 1985-2017
Publications (10 Years): 1

Top Venues

ICC

Publications

David Beckett, Sakir Sezer, John V. McCanny
New sensing technique for detecting application layer DDoS attacks targeting back-end database resources. ICC (2017)
Ye Lu, Changlin Chen, John V. McCanny, Sakir Sezer
Design of interlock-free combined allocators for Networks-on-Chip. SoCC (2012)
Ye Lu, John V. McCanny, Sakir Sezer
Generic Low-Latency NoC Router Architecture for FPGA Computing Systems. FPL (2011)
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny
QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers. IEEE Trans. Signal Process. 59 (4) (2011)
Ye Lu, John V. McCanny, Sakir Sezer
Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip. SoCC (2011)
Ye Lu, John V. McCanny, Sakir Sezer
The Impact of Global Routing on the Performance of NoCs in FPGAs. ReConFig (2011)
Liang Lu, John V. McCanny, Sakir Sezer
Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. IET Comput. Digit. Tech. 4 (5) (2010)
Ye Lu, Sakir Sezer, John V. McCanny
Advanced Multithreading Architecture with Hardware Based Scheduling. FPL (2010)
Yingxi Lu, Máire O'Neill, John V. McCanny
Evaluation of Random Delay Insertion against DPA on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4 (1) (2010)
Ye Lu, Sakir Sezer, John V. McCanny
TLM2.0 based timing accurate modeling method for complex NoC systems. ISCAS (2010)
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
High-Performance random data lookup for network processing. SoCC (2010)
Ye Lu, Sakir Sezer, John V. McCanny
Design and analysis of an advanced static blocked multithreading architecture. SoCC (2010)
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
DDR3 based lookup circuit for high-performance network processing. SoCC (2009)
Yongping Liu, Sakir Sezer, John V. McCanny
NFA decomposition and multiprocessing architecture for parallel regular expression processing. SoCC (2009)
Liang Lu, John V. McCanny, Sakir Sezer
Subpixel Interpolation Architecture for Multistandard Video Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 19 (12) (2009)
Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh
Is the differential frequency-based attack effective against random delay insertion? SiPS (2009)
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny
Modified givens rotations and their application to matrix inversion. ICASSP (2008)
Yingxi Lu, Máire O'Neill, John V. McCanny
Differential Power Analysis of a SHACAL-2 hardware implementation. ISCAS (2008)
Liang Lu, John V. McCanny, Sakir Sezer
Multi-standard sub-pixel interpolation architecture for video Motion Estimation. SoCC (2008)
Yingxi Lu, Máire O'Neill, John V. McCanny
FPGA implementation and analysis of random delay insertion countermeasure against DPA. FPT (2008)
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai
Reduced-complexity MSGR-based matrix inversion. SiPS (2008)
Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.
High performance IP lookup circuit using DDR SDRAM. SoCC (2008)
Roger F. Woods, John V. McCanny, John G. McWhirter
From Bit Level Systolic Arrays to HDTV Processor Chips. J. Signal Process. Syst. 53 (1-2) (2008)
Yen-Kuang Chen, David W. Lin, John V. McCanny, Edwin Hsing-Mean Sha
Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication. J. Signal Process. Syst. 51 (3) (2008)
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
Novel Content Addressable Memory Architecture for Adaptive Systems. AHS (2007)
Liang Lu, John V. McCanny, Sakir Sezer
Systolic Array Based Architecture for Variable Block-Size Motion Estimation. AHS (2007)
John V. McCanny, Sakir Sezer, Máire O'Neill
Exploring technology related design-space limitations of high performance network processing. ESSCIRC (2007)
Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns
A versatile content addressable memory architecture. SoCC (2007)
John V. McCanny
From Special Purpose VLSI Architectures to HDTV Processors and Gigabit Wireless Systems. DSP (2007)
Liang Lu, John V. McCanny, Sakir Sezer
Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. ASAP (2007)
Liang Lu, John V. McCanny, Sakir Sezer
Reconfigurable video motion estimation processor. SoCC (2007)
Ciaran McIvor, Máire McLoone, John V. McCanny
Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2006)
Neil Smyth, Máire McLoone, John V. McCanny
An Adaptable And Scalable Asymmetric Cryptographic Processor. ASAP (2006)
Neil Smyth, Máire McLoone, John V. McCanny
WLAN security processor. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2006)
Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny
Design and analysis of matching circuit architectures for a closest match lookup. IPDPS (2006)
John V. McCanny, Roger F. Woods, John G. McWhirter
From Bit Level Systolic Arrays to HDTV Processor Chips. ASAP (2006)
Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny
Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. AICT/ICIW (2006)
Zhaohui Liu, Kevin Dickson, John V. McCanny
Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2005)
Zhaohui Liu, Kevin Dickson, John V. McCanny
Hardware Design of Sphere Decoding for MIMO Systems. SoCC (2005)
Ciaran McIvor, Máire McLoone, John V. McCanny
High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. FPT (2005)
Máire McLoone, Ciaran McIvor, John V. McCanny
Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. FPT (2004)
Ciaran McIvor, Máire McLoone, John V. McCanny
FPGA Montgomery Multiplier Architectures - A Comparison. FCCM (2004)
Ciaran McIvor, Máire McLoone, John V. McCanny
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ISCAS (3) (2004)
Shahid Masud, John V. McCanny
Reusable silicon IP cores for discrete wavelet transform applications. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2004)
Swee Yeow Yap, John V. McCanny
A VLSI architecture for variable block size video motion estimation. IEEE Trans. Circuits Syst. II Express Briefs (7) (2004)
Zhaohui Liu, John V. McCanny
Implementation of adaptive beamforming based on QR decomposition for CDMA. ICASSP (2) (2003)
Zhaohui Liu, John V. McCanny, Gaye Lightbody, Richard L. Walke
Generic SoC QR array processor for adaptive beamforming. IEEE Trans. Circuits Syst. II Express Briefs 50 (4) (2003)
Zhaohui Liu, Kevin Dickson, John V. McCanny
A floating-point CORDIC based SVD processor. ASAP (2003)
Ciaran McIvor, Máire McLoone, John V. McCanny
A high-speed, low latency RSA decryption silicon core. ISCAS (4) (2003)
Máire McLoone, John V. McCanny
Very High Speed 17 Gbps SHACAL Encryption Architecture. FPL (2003)
Swee Yeow Yap, John V. McCanny
A VLSI Architecture for Advanced Video Coding Motion Estimation. ASAP (2003)
Máire McLoone, John V. McCanny
Rijndael FPGA Implementations Utilising Look-Up Tables. J. VLSI Signal Process. 34 (3) (2003)
Máire McLoone, John V. McCanny
Efficient single-chip implementation of SHA-384 and SHA-512. FPT (2002)
Kok Sing Yap, John V. McCanny
A mixed cost-function adaptive algorithm for ADSL time-domain equalization. ICC (2002)
Paul V. McCanny, Shahid Masud, John V. McCanny
Design and implementation of the symmetrically extended 2-D Wavelet Transform. ICASSP (2002)
Kok Sing Yap, John V. McCanny
A hybrid mixed cost-function TEQ initialization algorithm for ADSL modems. ICASSP (2002)
Paul V. McCanny, John V. McCanny, Shahid Masud
VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform. EUSIPCO (2002)
Shahid Masud, John V. McCanny
Design of Silicon IP Cores for Biorthogonal Wavelet Transforms. J. VLSI Signal Process. 29 (3) (2001)
Paul V. McCanny, Shahid Masud, John V. McCanny
An efficient architecture for the 2-D biorthogonal discrete wavelet transform. ICIP (3) (2001)
Zhaohui Liu, Gaye Lightbody, Richard L. Walke, Yi Hu, John V. McCanny
Generic scheduling methods for a linear QR array SoC processor. ICASSP (2001)
Máire McLoone, John V. McCanny
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. FPL (2001)
Máire McLoone, John V. McCanny
High Performance Single-Chip FPGA Rijndael Algorithm Implementations. CHES (2001)
Robert Hamill, John V. McCanny, Richard L. Walke
Online CORDIC algorithm and VLSI architecture for implementing QR-array processors. IEEE Trans. Signal Process. 48 (2) (2000)
Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny
Linear QR Architecture for a Single Chip Adaptive Beamformer. J. VLSI Signal Process. 24 (1) (2000)
Shahid Masud, John V. McCanny
Wavelet packet transforms for system-on-chip applications. ICASSP (2000)
Tiong Jiu Ding, John V. McCanny, Yunsheng Hu
Rapid design of application specific FFT cores. IEEE Trans. Signal Process. 47 (5) (1999)
Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny
Novel mapping of a linear QR architecture. ICASSP (1999)
Shahid Masud, John V. McCanny
Rapid design of discrete orthonormal wavelet transforms using silicon IP components. ICASSP (1999)
Shahid Masud, John V. McCanny
Rapid Design of Discrete Orthonormal Wavelet Transforms. International Workshop on Rapid System Prototyping (1998)
Jill K. Hunter, John V. McCanny
Discrete cosine transform generator for VLSI synthesis. ICASSP (1998)
Jill K. Hunter, John V. McCanny
Rapid design of discrete transform cores. EUSIPCO (1998)
David W. Trainor, Roger F. Woods, John V. McCanny
Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". J. VLSI Signal Process. 16 (1) (1997)
John V. McCanny, Douglas Ridge, Yi Hu, Jill K. Hunter
Hierarchical VHDL libraries for DSP ASIC design. ICASSP (1997)
B. D. E. Smith, John V. McCanny
Synthesisable high performance adaptive equaliser and Viterbi decoder for the Class-IV PRML channel. ICECS (1996)
Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
A 64-point Fourier transform chip for video motion compensation using phase correlation. IEEE J. Solid State Circuits 31 (11) (1996)
Colin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
Error analysis of FFT architectures for digital video applications. ICECS (1996)
Colin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods
A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. ASAP (1996)
Stephen E. McQuillan, John V. McCanny
A Systematic Methodology for the Design of High Performance Recursive Digital Filters. IEEE Trans. Computers 44 (8) (1995)
M. Yan, John V. McCanny, Yi Hu
VLSI architectures for vector quantization. J. VLSI Signal Process. 10 (1) (1995)
John V. McCanny, Yi Hu, M. Yan
Automated design of DSP array processor chips. ASAP (1994)
Stephen E. McQuillan, John V. McCanny
Fast VLSI algorithms for division and square root. J. VLSI Signal Process. 8 (2) (1994)
Stephen E. McQuillan, John V. McCanny, Robert Hamill
New algorithms and VLSI architectures for SRT division and square root. IEEE Symposium on Computer Arithmetic (1993)
M. Yan, John V. McCanny
Systolic inner product arrays with automatic word rounding. J. VLSI Signal Process. 4 (2-3) (1992)
B. P. McGovern, Roger F. Woods, John V. McCanny
The systematic design of high performance digital filters. ICASSP (1992)
Rajinder Jit Singh, John V. McCanny
High performance VLSI architecture for Wave Digital Filtering. J. VLSI Signal Process. 4 (4) (1992)
Stephen E. McQuillan, John V. McCanny
Algorithms and architectures for high performance recursive filtering. ASAP (1992)
John V. McCanny
On the use of most significant digit first arithmetic in the design of high performance DSP chips. Algorithms and Parallel VLSI Architectures (1991)
Stephen E. McQuillan, John V. McCanny
A VLSI architecture for multiplication, division and square root. ICASSP (1991)
Rajinder Jit Singh, John V. McCanny
A wave digital filter three-port adaptor with fine grained pipelining. ASAP (1991)
O. C. McNally, John V. McCanny, Roger F. Woods
A 40 megasample IIR filter chip. ASAP (1991)
O. C. McNally, William P. Marnane, John V. McCanny
Design and test of a bit parallel 2nd order IIR filter structure. ICASSP (1991)
O. C. McNally, John V. McCanny, Roger F. Woods
Design of a Highly Pipelined 2nd Order IIR Filter Chip. VLSI (1991)
Y. Hu, John V. McCanny, M. Yan
Systolic VLSI compiler (SVC) for high performance vector quantisation chips. ASAP (1990)
O. C. McNally, John V. McCanny, Roger F. Woods
Optimized bit level architectures for IIR filtering. ICCD (1990)
Rajinder Jit Singh, John V. McCanny
Systolic two-port adaptor for high performance wave digital filtering. ASAP (1990)
John V. McCanny, John G. McWhirter, Sun-Yuan Kung
The use of data dependence graphs in the design of bit-level systolic arrays. IEEE Trans. Acoust. Speech Signal Process. 38 (5) (1990)
Rajinder Jit Singh, John V. McCanny, Roger F. Woods
Pipelined two-port adaptor for wave digital filtering. ICASSP (1990)
M. Yan, John V. McCanny, Yi Hu
VLSI architectures for digital image coding. ICASSP (1990)
M. Yan, John V. McCanny
A bit-level systolic architecture for implementing a VQ tree search. J. VLSI Signal Process. 2 (3) (1990)
Simon C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny
A bit-level systolic architecture for very high performance IIR filters. ICASSP (1989)

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Publication Activity (10 Years)

Top Topics

Top Venues

John V. McCanny