John McAllister

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 28

Top Topics

Nearest Neighbour

Top Venues

J. Signal Process. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Michael Hart, John McAllister
Reconstructing Cut Quantum Circuits Maximising Fidelity between Quantum States. CF (2024)
Michael Hart, John McAllister
Quantum Circuit Cutting Minimising Loss of Qubit Entanglement. CF (2024)
Timoteo García Bertoa, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, John McAllister
Fault-Tolerant Neural Network Accelerators With Selective TMR. IEEE Des. Test 40 (2) (2023)
Viraj Singh Gaur, Vishal Sharma, John McAllister
Abusive adversarial agents and attack strategies in cyber-physical systems. CAAI Trans. Intell. Technol. 8 (1) (2023)
Jarlath Warner, Richard Gault, John McAllister
Optimised EMG pipeline for gesture classification. EMBC (2022)
Vishal Sharma, Blesson Varghese, John McAllister, Saraju P. Mohanty
Abusive Adversaries in 5G and Beyond IoT. IEEE Consumer Electron. Mag. 11 (4) (2022)
John McAllister
Editorial. J. Signal Process. Syst. 94 (8) (2022)
Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón
EMG Biometric Systems Based on Different Wrist-Hand Movements. IEEE Access 9 (2021)
John McAllister
Algorithms & Architectures at the Boundary of Signal Processing & Machine Learning. J. Signal Process. Syst. 93 (10) (2021)
Yun Wu, John McAllister
Configurable Quasi-Optimal Sphere Decoding for Scalable MIMO Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (6) (2021)
Yun Wu, John McAllister
Energy-Efficient Adaptive Modulated Fixed-Complexity Sphere Decoder. SiPS (2021)
John McAllister, Mike Polley, Roozbeh Jafari
The Applied Signal Processing Systems Technical Committee [In the Spotlight]. IEEE Signal Process. Mag. 38 (1) (2021)
Yun Wu, Peng Wang, John McAllister
Programmable Dataflow Accelerators: A 5G OFDM Modulation/Demodulation Case Study. ICASSP (2020)
Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón
Real-Time Embedded EMG Signal Analysis for Wrist-Hand Pose Identification. IEEE Trans. Signal Process. 68 (2020)
Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty
Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92 (10) (2020)
John McAllister, Michael Davis
Graph Coordination for Compact Representation of Regular Dataflow Structures. SiPS (2020)
Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty
Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92 (10) (2020)
Leo Rogers, John McAllister
Comparison of Exponentially Decreasing Vs. Polynomially Decreasing Objective Functions for Making Quantum Circuits Nearest Neighbour Compliant. SAMOS (2019)
Leo Rogers, John McAllister
Window Size Estimation for Nearest Neighbour Compliant Quantum Circuit Mapping. ISCAS (2019)
Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón
EMG Wrist-hand Motion Recognition System for Real-time Embedded Platform. ICASSP (2019)
Yun Wu, John McAllister
On Modified Squared Givens Rotations for Sphere Decoder Preprocessing. ICASSP (2019)
Sumit A. Raurale, John McAllister, Jesús Martínez del Rincón
Emg Acquisition and Hand Pose Classification for Bionic Hands from Randomly-Placed Sensors. ICASSP (2018)
Yun Wu, John McAllister
Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA. IEEE Trans. Parallel Distributed Syst. 29 (1) (2018)
Stephen Laide, John McAllister
Multicore distributed dictionary learning: A microarray gene expression biclustering case study. ICASSP (2017)
Yun Wu, John McAllister
Bounded Selective Spanning With Extended Fast Enumeration for MIMO-OFDM Systems Detection. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Peng Wang, John McAllister
Streaming Elements for FPGA Signal and Image Processing Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
John McAllister, Máire O'Neill, Maxime Pelcat
Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies. J. Signal Process. Syst. 84 (3) (2016)
Matthew Milford, John McAllister
Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels. IEEE Trans. Signal Process. 64 (16) (2016)
John McAllister, David Guevorkian, Hartwig Jeschke, Mihai Sima
Guest Editorial: Special Issue on Embedded Computer Systems: Architectures, Modeling and Simulation. Int. J. Parallel Program. 43 (1) (2015)
Yun Wu, John McAllister
FPGA-based Tabu search for detection in large-scale MIMO systems. SiPS (2014)
Yun Wu, John McAllister
Bounded selective spanning with extended fast enumeration for MIMO-OFDM systems detection. EUSIPCO (2013)
Peng Wang, John McAllister, Yun Wu
Soft-core stream processing on FPGA: An FFT case study. ICASSP (2013)
Peng Wang, John McAllister, Yun Wu
Software defined FFT architecture for IEEE 802.11ac. GlobalSIP (2013)
Yun Wu, John McAllister, Peng Wang
High performance real-time Pre-Processing for Fixed-Complexity Sphere Decoder. GlobalSIP (2013)
John McAllister, Luigi Carro, Skevos Evripidou
Guest Editorial: Special Issue on 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI). Int. J. Parallel Program. 41 (2) (2013)
Ciara Moore, Neil Hanley, John McAllister, Máire O'Neill, Elizabeth O'Sullivan, Xiaolin Cao
Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE. Financial Cryptography Workshops (2013)
Peng Wang, John McAllister
Soft-core stream processor for sliding window applications. SiPS (2013)
Matthew Milford, John McAllister
Memory-centric VDF graph transformations for practical FPGA implementation. ESTIMedia (2012)
John McAllister, Shuvra S. Bhattacharyya
Preface. ICSAMOS (2012)
Matthew Milford, John McAllister
Automatic FPGA synthesis of memory intensive C-based kernels. ICSAMOS (2012)
Matthew Milford, John McAllister
Valved dataflow for FPGA memory hierarchy synthesis. ICASSP (2012)
Xuezheng Chu, John McAllister
Software-Defined Sphere Decoding for FPGA-Based MIMO Detection. IEEE Trans. Signal Process. 60 (11) (2012)
Xuezheng Chu, John McAllister, Roger F. Woods
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection. ARC (2011)
Chengwei Zheng, John McAllister, Yun Wu
A kernel interleaved scheduling method for streaming applications on soft-core vector processors. ICSAMOS (2011)
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny
QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers. IEEE Trans. Signal Process. 59 (4) (2011)
C. Zheng, Xuezheng Chu, John McAllister, Roger F. Woods
Real-Valued Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO Systems. IEEE Trans. Signal Process. 59 (9) (2011)
Xuezheng Chu, John McAllister
FPGA based soft-core SIMD processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder case study. FPT (2010)
Scott Fischaber, Roger F. Woods, John McAllister
SoC Memory Hierarchy Derivation from Dataflow Graphs. J. Signal Process. Syst. 60 (3) (2010)
John McAllister
Evolutionary requirements for next-generation dataflow-based FPGA system design. EUSIPCO (2009)
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny
Modified givens rotations and their application to matrix inversion. ICASSP (2008)
Stephen McKeown, Roger F. Woods, John McAllister
Power efficient dynamic-range utilisation for DSP on FPGA. SiPS (2008)
John McAllister
Introduction to System Level Design for Heterogeneous Systems. SAMOS (2008)
Scott Fischaber, John McAllister, Roger F. Woods
Memory-Centric Hardware Synthesis from Dataflow Models. SAMOS (2008)
Stephen McKeown, Roger F. Woods, John McAllister
Power efficient DSP datapath configuration methodology for FPGA. FPL (2008)
Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai
Reduced-complexity MSGR-based matrix inversion. SiPS (2008)
Erdem Motuk, Roger F. Woods, Stefan Bilbao, John McAllister
Design Methodology for Real-Time FPGA-Based Sound Synthesis. IEEE Trans. Signal Process. 55 (12) (2007)
John McAllister, Roger F. Woods, Scott Fischaber, E. Malins
Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. J. Syst. Archit. 53 (8) (2007)
Scott Fischaber, Roger F. Woods, John McAllister
SOC Memory Hierarchy Derivation from Dataflow Graphs. SiPS (2007)
Scott Fischaber, John McAllister, Roger F. Woods, E. Malins
Muir Hardware Synthesis for Multimedia Applications. ESTIMedia (2006)
John McAllister, Roger F. Woods, Richard L. Walke, Darren Gerard Reilly
Multidimensional DSP Core Synthesis for FPGA. J. VLSI Signal Process. 43 (2-3) (2006)
Scott Fischaber, R. Hasson, John McAllister, Roger F. Woods
FPGA Core Network Implementation and Optimization: A Case Study. FPT (2005)
Jasmine Lam, John McAllister, Jennifer Dudley
Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs. FCCM (2005)
Darren Gerard Reilly, Roger F. Woods, John McAllister, Richard L. Walke
Rapid generation of hardware functionality in heterogeneous platforms [FPGA implementation applications]. ICASSP (5) (2005)
John McAllister, Roger F. Woods, Darren Gerard Reilly, Scott Fischaber, R. Hasson
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. SAMOS (2005)
John McAllister, Roger F. Woods, Richard L. Walke
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. SAMOS (2004)