Neil Hanley

Publication Activity (10 Years)

Years Active: 2009-2022
Publications (10 Years): 16

Top Topics

Countermeasures

Homomorphic Encryption

Top Venues

IEEE Trans. Computers

J. Cryptogr. Eng.

Publications

Anh-Tuan Hoang, Neil Hanley, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill
Stacked Ensemble Models Evaluation on DL Based SCA. ICSBT/SECRYPT (Revised Selected Papers) (2022)
Anh-Tuan Hoang, Neil Hanley, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill
Stacked Ensemble Model for Enhancing the DL based SCA. SECRYPT (2022)
Chongyan Gu, Weiqiang Liu, Yijun Cui, Neil Hanley, Máire O'Neill, Fabrizio Lombardi
A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl
SCA secure and updatable crypto engines for FPGA SoC bitstream decryption: extended version. J. Cryptogr. Eng. 11 (3) (2021)
Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Máire O'Neill
A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs. J. Cryptogr. Eng. 11 (3) (2021)
Anh-Tuan Hoang, Neil Hanley, Máire O'Neill
Plaintext: A Missing Feature for Enhancing the Power of Deep Learning in Side-Channel Analysis? Breaking multiple layers of side-channel countermeasures. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020 (4) (2020)
Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Máire O'Neill
A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs. ASHES@CCS (2019)
Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl
SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption. ASHES@CCS (2019)
Chongyan Gu, Weiqiang Liu, Neil Hanley, Robert Hesselbarth, Máire O'Neill
A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations. IEEE Trans. Computers 68 (2) (2019)
Qingqing Ma, Chongyan Gu, Neil Hanley, Chenghua Wang, Weiqiang Liu, Máire O'Neill
A machine learning attack resistant multi-PUF design on FPGA. ASP-DAC (2018)
Robert Hesselbarth, Florian Wilde, Chongyan Gu, Neil Hanley
Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs. HOST (2018)
Chongyan Gu, Neil Hanley, Máire O'Neill
FPGA-based strong PUF with increased uniqueness and entropy properties. ISCAS (2017)
Ciara Rafferty, Máire McLoone, Neil Hanley
Evaluation of Large Integer Multiplication Methods on Hardware. IEEE Trans. Computers 66 (8) (2017)
Chongyan Gu, Neil Hanley, Máire O'Neill
Improved Reliability of FPGA-Based PUF Identification Generator Design. ACM Trans. Reconfigurable Technol. Syst. 10 (3) (2017)
Chongyan Gu, Yijun Cui, Neil Hanley, Máire O'Neill
Novel lightweight FF-APUF design for FPGA. SoCC (2016)
Xiaolin Cao, Ciara Moore, Máire O'Neill, Elizabeth O'Sullivan, Neil Hanley
Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption. IEEE Trans. Computers 65 (9) (2016)
Hyunjin Ahn, Neil Hanley, Máire O'Neill, Dong-Guk Han
An Improved Second-Order Power Analysis Attack Based on a New Refined Expecter - - Case Study on Protected AES -. WISA (2015)
Richard Gilmore, Neil Hanley, Máire O'Neill
Neural network based attack on a masked implementation of AES. HOST (2015)
Neil Hanley, HeeSeok Kim, Michael Tunstall
Exploiting Collisions in Addition Chain-Based Exponentiation Algorithms Using a Single Trace. CT-RSA (2015)
Philip Hodgers, Neil Hanley, Máire O'Neill
Pre-processing power traces to defeat random clocking countermeasures. ISCAS (2015)
Xiaolin Cao, Ciara Moore, Máire O'Neill, Neil Hanley, Elizabeth O'Sullivan
High-Speed Fully Homomorphic Encryption Over the Integers. Financial Cryptography Workshops (2014)
Ciara Moore, Máire O'Neill, Neil Hanley, Elizabeth O'Sullivan
Accelerating integer-based fully homomorphic encryption using Comba multiplication. SiPS (2014)
Qizhi Tian, Máire O'Neill, Neil Hanley
Can leakage models be more efficient? non-linear models in side channel attacks. WIFS (2014)
Neil Hanley, Máire O'Neill, Michael Tunstall, William P. Marnane
Empirical evaluation of multi-device profiling side-channel attacks. SiPS (2014)
Ciara Moore, Neil Hanley, John McAllister, Máire O'Neill, Elizabeth O'Sullivan, Xiaolin Cao
Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE. Financial Cryptography Workshops (2013)
Xiaolin Cao, Ciara Moore, Máire O'Neill, Elizabeth O'Sullivan, Neil Hanley
Accelerating Fully Homomorphic Encryption over the Integers with Super-size Hardware Multiplier and Modular Reduction. IACR Cryptol. ePrint Arch. 2013 (2013)
Philip Hodgers, Neil Hanley, Máire O'Neill
Pre-processing power traces with a phase-sensitive detector. HOST (2013)
Neil Hanley, HeeSeok Kim, Michael Tunstall
Exploiting Collisions in Addition Chain-based Exponentiation Algorithms. IACR Cryptol. ePrint Arch. 2012 (2012)
Neil Hanley, Máire O'Neill
Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers. ISVLSI (2012)
Neil Hanley, Michael Tunstall, William P. Marnane
Using templates to distinguish multiplications from squaring operations. Int. J. Inf. Sec. 10 (4) (2011)
Neil Hanley, Michael Tunstall, William P. Marnane
Using Templates to Distinguish Multiplications from Squaring Operations. IACR Cryptol. ePrint Arch. 2011 (2011)
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O'Neill, William P. Marnane
FPGA Implementations of the Round Two SHA-3 Candidates. FPL (2010)
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O'Neill, William P. Marnane
A Hardware Wrapper for the SHA-3 Hash Algorithms. IACR Cryptol. ePrint Arch. 2010 (2010)
Jean-François Gallais, Johann Großschädl, Neil Hanley, Markus Kasper, Marcel Medwed, Francesco Regazzoni, Jörn-Marc Schmidt, Stefan Tillich, Marcin Wójcik
Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software. INTRUST (2010)
Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan, William P. Marnane
FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash. IACR Cryptol. ePrint Arch. 2009 (2009)
Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan, William P. Marnane
FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash. DSD (2009)
Neil Hanley, Michael Tunstall, William P. Marnane
Unknown Plaintext Template Attacks. WISA (2009)