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A Hardware Wrapper for the SHA-3 Hash Algorithms.
Brian Baldwin
Andrew Byrne
Liang Lu
Mark Hamilton
Neil Hanley
Máire O'Neill
William P. Marnane
Published in:
IACR Cryptol. ePrint Arch. (2010)
Keyphrases
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significant improvement
computational efficiency
hardware and software
data structure
computational complexity
worst case
computationally efficient
times faster
black box
parallel architectures
website
low cost
optimization problems
orders of magnitude
learning algorithm
parallel processors