FPGA Implementations of the Round Two SHA-3 Candidates.
Brian BaldwinAndrew ByrneLiang LuMark HamiltonNeil HanleyMáire O'NeillWilliam P. MarnanePublished in: FPL (2010)
Keyphrases
- software implementation
- hardware architectures
- high speed
- hardware implementation
- field programmable gate array
- low cost
- signal processing
- efficient implementation
- real time image processing
- real time
- heuristic rules
- hardware architecture
- digital signal
- verilog hdl
- general purpose processors
- power reduction
- data acquisition
- general purpose
- computational complexity