Dur-e-Shahwar Kundi

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 22

Top Topics

Pareto Optimality

Top Venues

IACR Cryptol. ePrint Arch.

IEEE Trans. Circuits Syst. II Express Briefs

ICSBT/SECRYPT (Revised Selected Papers)

Publications

Ziying Ni, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu
HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining. IEEE Trans. Computers 72 (12) (2023)
Yuantuo Zhang, Yijun Cui, Ziying Ni, Dur-e-Shahwar Kundi, Dongsheng Liu, Weiqiang Liu
A Lightweight and Efficient Schoolbook Polynomial Multiplier for Saber. ISCAS (2022)
Anh-Tuan Hoang, Neil Hanley, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill
Stacked Ensemble Models Evaluation on DL Based SCA. ICSBT/SECRYPT (Revised Selected Papers) (2022)
Chuanchao Lu, Yijun Cui, Yang Li, Dur-e-Shahwar Kundi, Chenghua Wang, Weiqiang Liu
Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem. ISCAS (2022)
Dur-e-Shahwar Kundi, Ayesha Khalid, Song Bian, Chenghua Wang, Máire O'Neill, Weiqiang Liu
AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications. IEEE Internet Things J. 9 (13) (2022)
Dur-e-Shahwar Kundi, Yuqing Zhang, Chenghua Wang, Ayesha Khalid, Máire O'Neill, Weiqiang Liu
Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs. IEEE Trans. Emerg. Top. Comput. 10 (4) (2022)
Ziying Ni, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu
A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Anh-Tuan Hoang, Neil Hanley, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill
Stacked Ensemble Model for Enhancing the DL based SCA. SECRYPT (2022)
Ziying Ni, Ayesha Khalid, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu
Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator. IACR Cryptol. ePrint Arch. 2022 (2022)
Ziying Ni, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu
A High-Performance SIKE Hardware Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30 (6) (2022)
Song Bian, Dur-e-Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, Takashi Sato
APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Ziying Ni, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu
High-Performance Systolic Array Montgomery Multiplier for SIKE. ISCAS (2021)
Kan Yao, Dur-e-Shahwar Kundi, Chenghua Wang, Máire O'Neill, Weiqiang Liu
Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off. ISCAS (2021)
Song Bian, Dur-e-Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, Takashi Sato
APAS: Application-Specific Accelerators for RLWE-based Homomorphic Linear Transformations. IACR Cryptol. ePrint Arch. 2021 (2021)
Dur-e-Shahwar Kundi, Ayesha Khalid, Arshad Aziz, Chenghua Wang, Máire O'Neill, Weiqiang Liu
Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3. IEEE Trans. Circuits Syst. (12) (2020)
Yuqing Zhang, Chenghua Wang, Dur-e-Shahwar Kundi, Ayesha Khalid, Máire O'Neill, Weiqiang Liu
An Efficient and Parallel R-LWE Cryptoprocessor. IEEE Trans. Circuits Syst. II Express Briefs (5) (2020)
Dur-e-Shahwar Kundi, Song Bian, Ayesha Khalid, Chenghua Wang, Máire O'Neill, Weiqiang Liu
AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem. ISCAS (2020)
Majida Kazmi, Arshad Aziz, Dur-e-Shahwar Kundi
A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications. Circuits Syst. Signal Process. 38 (10) (2019)
Razia Zia, Pervez Akhtar, Arshad Aziz, Dur-e-Shahwar Kundi
Multi-resolution transforms-based hybrid feature extraction technique for differentiating glioma grades. Int. J. Wavelets Multiresolution Inf. Process. 16 (6) (2018)
Razia Zia, Pervez Akhtar, Arshad Aziz, Maroof Ali Shah, Dur-e-Shahwar Kundi
Non Sub-sampled Contourlet Transform Based Feature Extraction Technique for Differentiating Glioma Grades Using MRI Images. Australasian Conference on Artificial Intelligence (2017)
Dur-e-Shahwar Kundi, Arshad Aziz, Nassar Ikram
A high performance ST-Box based unified AES encryption/decryption architecture on FPGA. Microprocess. Microsystems 41 (2016)
Dur-e-Shahwar Kundi, Arshad Aziz
A low-power SHA-3 designs using embedded digital signal processing slice on FPGA. Comput. Electr. Eng. 55 (2016)
Dur-e-Shahwar Kundi, Arshad Aziz, Majida Kazmi
-box implementation for 128-bit AES on FPGA. Secur. Commun. Networks 8 (9) (2015)
Aisha Malik, Arshad Aziz, Dur-e-Shahwar Kundi, Moiz Akhter
Software implementation of Standard Hash Algorithm (SHA-3) Keccak on Intel core-i5 and Cavium Networks Octeon Plus embedded platform. MECO (2013)
Dur-e-Shahwar Kundi, Arshad Aziz, Nassar Ikram
Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA. Inf. Process. Lett. 110 (10) (2010)