Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA.
Dur-e-Shahwar KundiArshad AzizNassar IkramPublished in: Inf. Process. Lett. (2010)
Keyphrases
- efficient implementation
- hardware implementation
- field programmable gate array
- fpga device
- s box
- hardware design
- hardware architecture
- fpga implementation
- resource allocation
- reconfigurable hardware
- active set
- image processing algorithms
- highly parallel
- resource constraints
- parallel architecture
- face recognition
- fault model
- secret key
- efficient processing
- image processing
- cryptographic algorithms
- xilinx virtex