-box implementation for 128-bit AES on FPGA.
Dur-e-Shahwar KundiArshad AzizMajida KazmiPublished in: Secur. Commun. Networks (2015)
Keyphrases
- advanced encryption standard
- hardware implementation
- s box
- hardware architecture
- efficient implementation
- fpga hardware
- encryption algorithms
- bit parallel
- hardware architectures
- single chip
- hardware design
- block cipher
- real time
- dedicated hardware
- low cost
- fpga technology
- fpga implementation
- xilinx virtex
- fpga device
- digital signal
- general purpose