Máire McLoone

Publication Activity (10 Years)

Years Active: 2001-2017
Publications (10 Years): 1

Top Venues

IEEE Trans. Computers

Queen's University Belfast, UK (PHD)

Education History

Queen's University Belfast, UK

PHD

Publications

Ciara Rafferty, Máire McLoone, Neil Hanley
Evaluation of Large Integer Multiplication Methods on Hardware. IEEE Trans. Computers 66 (8) (2017)
Clare McGrath, Ghazanfar Ali Safdar, Máire McLoone
Identity Based Public Key Exchange (IDPKE) for Wireless Ad Hoc Networks. SECRYPT (2007)
Máire McLoone, Matthew J. B. Robshaw
New Architectures for Low-Cost Public Key Cryptography on RFID Tags. ISCAS (2007)
Máire McLoone, Ciaran McIvor
High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. J. VLSI Signal Process. 47 (1) (2007)
Nicolas Sklavos, Máire McLoone, Xinmiao Zhang
MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. Mob. Networks Appl. 12 (4) (2007)
Máire McLoone, Matthew J. B. Robshaw
Public Key Cryptography and RFID Tags. CT-RSA (2007)
Ciaran McIvor, Máire McLoone, John V. McCanny
Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2006)
Neil Smyth, Máire McLoone, John V. McCanny
An Adaptable And Scalable Asymmetric Cryptographic Processor. ASAP (2006)
Neil Smyth, Máire McLoone, John V. McCanny
WLAN security processor. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2006)
Ghazanfar Ali Safdar, Clare McGrath, Máire McLoone
Limitations of existing wireless networks authentication and key management techniques for MANETs. ISCN (2006)
P. Moore, Máire McLoone, Sakir Sezer
Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. AICT/SAPIR/ELETE (2005)
Ciaran McIvor, Máire McLoone, John V. McCanny
High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. FPT (2005)
Máire McLoone, Ciaran McIvor, Aidan Savage
High-Speed Hardware Architectures of the Whirlpool Hash Function. FPT (2005)
Máire McLoone, Ciaran McIvor, John V. McCanny
Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. FPT (2004)
Ciaran McIvor, Máire McLoone, John V. McCanny
FPGA Montgomery Multiplier Architectures - A Comparison. FCCM (2004)
Ciaran McIvor, Máire McLoone, John V. McCanny
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ISCAS (3) (2004)
Ciaran McIvor, Máire McLoone, John V. McCanny
A high-speed, low latency RSA decryption silicon core. ISCAS (4) (2003)
Máire McLoone, John V. McCanny
Very High Speed 17 Gbps SHACAL Encryption Architecture. FPL (2003)
Máire McLoone, John V. McCanny
Rijndael FPGA Implementations Utilising Look-Up Tables. J. VLSI Signal Process. 34 (3) (2003)
Máire McLoone, John V. McCanny
Efficient single-chip implementation of SHA-384 and SHA-512. FPT (2002)
Máire McLoone, John V. McCanny
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. FPL (2001)
Máire McLoone, John V. McCanny
High Performance Single-Chip FPGA Rijndael Algorithm Implementations. CHES (2001)

Máire McLoone.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Máire McLoone