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Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE.
Ciara Moore
Neil Hanley
John McAllister
Máire O'Neill
Elizabeth O'Sullivan
Xiaolin Cao
Published in:
Financial Cryptography Workshops (2013)
Keyphrases
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floating point
hardware implementation
signal processing
integer valued
digital signal processing
real time
low cost
real time image processing
website
case study
neural network
image processing
high speed
low power
real numbers
systolic array