Bevan M. Baas

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 23

Top Topics

Processor Array

Arithmetic Coder

Motion Estimation

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Satyabrata Sarangi, Bevan M. Baas
Energy-efficient canonical Huffman decoders on many-core processor arrays and FPGAs. Integr. 88 (2023)
Thomas Abbott, Bevan M. Baas
A Scalable JPEG Encoder on a Many-Core Array. MCSoC (2023)
Shifu Wu, Bevan M. Baas
Many-Core Display Stream Compression Decoders With Simplified Pixel Prediction. MWSCAS (2023)
Renjie Chen, Aaron Stillmaker, Bevan M. Baas
Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder. VLSI-SoC (2022)
Peiyao Shi, Aaron Stillmaker, Bevan M. Baas
Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array. MCSoC (2022)
Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, Bevan M. Baas
A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency. VLSI-SoC (2022)
Shifu Wu, Bevan M. Baas
Display Stream Compression Decoders for Fine-Grained Many-Core Processor Arrays. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Shifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution. A-SSCC (2021)
Shifu Wu, Bevan M. Baas
Indexed Color History Many-Core Engines for Display Stream Compression Decoders. ICECS (2020)
Aaron Stillmaker, Brent Bohnenstiehl, Lucas Stillmaker, Bevan M. Baas
Scalable energy-efficient parallel sorting on a fine-grained many-core processor array. J. Parallel Distributed Comput. 138 (2020)
Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty
Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92 (10) (2020)
Tokunbo Ogunfunmi, John McAllister, Bevan M. Baas, Mrityunjoy Chakraborty
Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop. J. Signal Process. Syst. 92 (10) (2020)
Aaron Stillmaker, Bevan M. Baas
Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81]. Integr. 67 (2019)
Shifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas
Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding. ACSSC (2018)
Shifu Wu, Bevan M. Baas
A Low-Cost Slice Interleaving DSC Decoder Architecture for Real-Time 8K Video Decoding. MWSCAS (2018)
Jon J. Pimentel, Brent Bohnenstiehl, Bevan M. Baas
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Michael Braly, Aaron Stillmaker, Bevan M. Baas
A configurable H.265-compatible motion estimation accelerator architecture for realtime 4K video encoding in 65 nm CMOS. DSC (2017)
Aaron Stillmaker, Bevan M. Baas
Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm. Integr. 58 (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications. IEEE Micro 37 (2) (2017)
Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
KiloCore: A 32-nm 1000-Processor Computational Array. IEEE J. Solid State Circuits 52 (4) (2017)
Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
KiloCore: A 32 nm 1000-processor array. Hot Chips Symposium (2016)
Brent Bohnenstiehl, Aaron Stillmaker, Jon J. Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo, Bevan M. Baas
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array. VLSI Circuits (2016)
Jon J. Pimentel, Aaron Stillmaker, Brent Bohnenstiehl, Bevan M. Baas
Area efficient backprojection computation with reduced floating-point word width for SAR image formation. ACSSC (2015)
Bin Liu, Mohammad H. Foroozannejad, Soheil Ghiasi, Bevan M. Baas
Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling. MWSCAS (2015)
Brent Bohnenstiehl, Bevan M. Baas
A software LDPC decoder implemented on a many-core array of programmable processors. ACSSC (2015)
Bin Liu, Brent Bohnenstiehl, Bevan M. Baas
Scalable hardware-based power management for many-core systems. ACSSC (2014)
Zhibin Xiao, Bevan M. Baas
Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi
Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (5) (2014)
Jon J. Pimentel, Bevan M. Baas
Hybrid floating-point modules with low area overhead on a fine-grained processing core. ACSSC (2014)
Anh Thien Tran, Bevan M. Baas
Achieving High-Performance On-Chip Networks With Shared-Buffer Routers. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Bin Liu, Bevan M. Baas
Parallel AES Encryption Engines for Many-Core Processor Arrays. IEEE Trans. Computers 62 (3) (2013)
Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas
LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization. VLSI Design 2013 (2013)
Aaron Stillmaker, Lucas Stillmaker, Bevan M. Baas
Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array. ICPADS (2012)
Zhibin Xiao, Bevan M. Baas
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. VLSI-SoC (Selected Papers) (2012)
Zhibin Xiao, Bevan M. Baas
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture. VLSI-SoC (2012)
Zhibin Xiao, Stephen Le, Bevan M. Baas
A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform. ACSCC (2011)
Houshmand Shirani-mehr, Tinoosh Mohsenin, Bevan M. Baas
A reduced routing network architecture for partial parallel LDPC decoders. ACSCC (2011)
Anh Thien Tran, Bevan M. Baas
RoShaQ: High-performance on-chip router with shared queues. ICCD (2011)
Zhibin Xiao, Bevan M. Baas
A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System. IEEE Trans. Circuits Syst. Video Technol. 21 (7) (2011)
Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas
Low power LDPC decoder with efficient stopping scheme for undecodable blocks. ISCAS (2011)
Bin Liu, Bevan M. Baas
A high-performance area-efficient AES cipher on a many-core platform. ACSCC (2011)
Zhiyi Yu, Bevan M. Baas
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 18 (5) (2010)
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (6) (2010)
Tinoosh Mohsenin, Bevan M. Baas
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders. J. Signal Process. Syst. 61 (3) (2010)
Dean Truong, Bevan M. Baas
Circuit modeling for practical many-core architecture design exploration. DAC (2010)
Tinoosh Mohsenin, Dean Nguyen Truong, Bevan M. Baas
A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2010)
Tinoosh Mohsenin, Dean Nguyen Truong, Bevan M. Baas
Multi-Split-Row Threshold Decoding Implementations for LDPC Codes. ISCAS (2009)
Anthony T. Jacobson, Dean Nguyen Truong, Bevan M. Baas
The Design of a Reconfigurable Continuous-flow Mixed-radix FFT Processor. ISCAS (2009)
Anh Thien Tran, Dean Truong, Bevan M. Baas
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. NOCS (2009)
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors. ISCAS (2009)
Dean Nguyen Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Christine Watnik, Anh Thien Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul Vincent Mejia, Bevan M. Baas
A 167-Processor Computational Platform in 65 nm CMOS. IEEE J. Solid State Circuits 44 (4) (2009)
Tinoosh Mohsenin, Dean Truong, Bevan M. Baas
An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes. ICC (2009)
Zhiyi Yu, Bevan M. Baas
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 17 (1) (2009)
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Dean Truong, Tinoosh Mohsenin, Bevan M. Baas
AsAP: An Asynchronous Array of Simple Processors. IEEE J. Solid State Circuits 43 (3) (2008)
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas
Architecture and Evaluation of an Asynchronous Array of Simple Processors. J. Signal Process. Syst. 53 (3) (2008)
Wayne H. Cheng, Bevan M. Baas
Dynamic voltage and frequency scaling circuits with two supply voltages. ISCAS (2008)
Tinoosh Mohsenin, Pascal Urard, Bevan M. Baas
A thresholding algorithm for improved Split-Row decoding of LDPC codes. ACSCC (2008)
Zhibin Xiao, Bevan M. Baas
A high-performance parallel CAVLC encoder on a fine-grained many-core system. ICCD (2008)
Zhiyi Yu, Bevan M. Baas
A low-area interconnect architecture for chip multiprocessors. ISCAS (2008)
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
A complete real-time 802.11a baseband receiver implemented on an array of programmable processors. ACSCC (2008)
Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung
AsAP: A Fine-Grained Many-Core Platform for DSP Applications. IEEE Micro 27 (2) (2007)
Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. 15 (10) (2007)
Tinoosh Mohsenin, Bevan M. Baas
High-Throughput LDPC Decoders Using A Multiple Split-Row Method. ICASSP (2) (2007)
Michael J. Meeuwsen, Zhiyi Yu, Bevan M. Baas
A Shared Memory Module for Asynchronous Arrays of Processors. EURASIP J. Embed. Syst. 2007 (2007)
Tinoosh Mohsenin, Bevan M. Baas
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. ICCD (2006)
Zhiyi Yu, Bevan M. Baas
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. ISVLSI (2006)
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas
An asynchronous array of simple processors for dsp applications. ISSCC (2006)
Zhiyi Yu, Bevan M. Baas
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. ICCD (2006)
Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric W. Work, Jeremy W. Webb, Michael A. Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin
Hardware and applications of AsAP: An asynchronous array of simple processors. Hot Chips Symposium (2006)
Bevan M. Baas
A generalized cached-FFT algorithm. ICASSP (5) (2005)
Bevan M. Baas
A low-power, high-performance, 1024-point FFT processor. IEEE J. Solid State Circuits 34 (3) (1999)
Bevan M. Baas
A 9.5 mW 330 μsec 1024-point FFT processor. CICC (1998)