Wei Zhang

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 92

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

CoRR

FPL

Publications

Jiandong Mu, Mengdi Wang, Feiwen Zhu, Jun Yang, Wei Lin, Wei Zhang
Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Guangyu Hu, Jianheng Tang, Changyuan Yu, Wei Zhang, Hongce Zhang
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction. ASPDAC (2024)
Enlai Li, Sharad Sinha, Wei Zhang
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Lan Chen, Dong Li, Xiao Wang, Pengpeng Shao, Wei Zhang, Yaowei Wang, Yonghong Tian, Jin Tang
Retain, Blend, and Exchange: A Quality-aware Spatial-Stereo Fusion Approach for Event Stream Recognition. CoRR (2024)
Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. CoRR (2024)
Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. FPGA (2024)
Fubing Mao, Yapu Guo, Xiaofei Liao, Hai Jin, Wei Zhang, Haikun Liu, Long Zheng, Xu Liu, Zihan Jiang, Xiaohua Zheng
Accelerating Loop-Oriented RTL Simulation With Code Instrumentation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang
PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. DAC (2023)
Zihan Jiang, Fubing Mao, Yapu Guo, Xu Liu, Haikun Liu, Xiaofei Liao, Hai Jin, Wei Zhang
ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy. DAC (2023)
Yun Liang, Wei Zhang, Stephen Neuendorffer, Wayne Luk
Special Issue: "AI Acceleration on FPGAs". ACM Trans. Embed. Comput. Syst. 22 (6) (2023)
Guangyu Hu, Wei Zhang, Hongce Zhang
NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking. MLCAD (2023)
Afzal Ahmad, Zhiyao Xie, Wei Zhang
PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search. DAC (2023)
Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. DATE (2023)
Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. FCCM (2023)
Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA (2023)
Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. DAC (2021)
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD (2021)
Zhe Lin, Sharad Sinha, Wei Zhang
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL (2020)
Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. ASP-DAC (2020)
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR (2020)
Zuomin Zhu, Wei Zhang, Vivek Chaturvedi, Amit Kumar Singh
Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (3) (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. CoRR (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power. CoRR (2020)
Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. ACM Trans. Reconfigurable Technol. Syst. 13 (3) (2020)
Zhe Lin, Wei Zhang, Sharad Sinha
Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA. CoRR (2020)
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. CoRR (2020)
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. CoRR (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. CoRR (2020)
Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. ASP-DAC (2020)
Wenjian He, Sanjeev Das, Wei Zhang, Yang Liu
BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information. ACM Trans. Embed. Comput. Syst. 19 (1) (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. FCCM (2019)
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD (2019)
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA (2019)
Shuo Wang, Yun Liang, Wei Zhang
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications. HPCA (2019)
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC (2019)
Mohammad Tahghighi, Wei Zhang
Accelerate pattern recognition for cyber security analysis. ASP-DAC (2019)
Chi Fung Brian Fong, Jiandong Mu, Wei Zhang
A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA. ISVLSI (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Zhe Lin, Sharad Sinha, Wei Zhang
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (9) (2019)
Liang Feng, Hiroaki Igarashi, Seiya Shibata, Yuki Kobayashi, Takashi Takenaka, Wei Zhang
Real-Time Detection and Tracking Using Hybrid DNNs and Space-Aware Color Feature: From Algorithm to System. ACPR (1) (2019)
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR (2019)
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE (2019)
Hao Liang, Sharad Sinha, Wei Zhang
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (2) (2018)
Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. FPL (2018)
Wei Zhang, Nan Guan, Lei Ju, Weichen Liu
Analyzing Data Cache Related Preemption Delay With Multiple Preemptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Wenjian He, Wei Zhang, Sanjeev Das, Yang Liu
SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution. ICCD (2018)
Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. FCCM (2018)
Sanjeev Das, Bihuan Chen, Mahinthan Chandramohan, Yang Liu, Wei Zhang
ROPSentry: Runtime defense against ROP attacks using hardware performance counters. Comput. Secur. 73 (2018)
Yun Liang, Shuo Wang, Wei Zhang
FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs. IEEE Trans. Computers 67 (12) (2018)
Weichen Liu, Lei Yang, Weiwen Jiang, Liang Feng, Nan Guan, Wei Zhang, Nikil D. Dutt
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip. IEEE Trans. Computers 67 (12) (2018)
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. IEEE Trans. Multi Scale Comput. Syst. 4 (2) (2018)
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam
Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs. FCCM (2017)
Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. ICCAD (2017)
Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
HeteroSim: A Heterogeneous CPU-FPGA Simulator. IEEE Comput. Archit. Lett. 16 (1) (2017)
Shuo Wang, Yun Liang, Wei Zhang
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs. DAC (2017)
Tao Luo, Hao Liang, Wei Zhang, Bingsheng He, Douglas L. Maskell
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency. IEEE Trans. Circuits Syst. II Express Briefs (1) (2017)
Wenjian He, Sanjeev Das, Wei Zhang, Yang Liu
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries. DAC (2017)
Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam
Dynamic module partitioning for library based placement on heterogeneous FPGAs. RTCSA (2017)
Zuomin Zhu, Vivek Chaturvedi, Amit Kumar Singh, Wei Zhang, Yingnan Cui
Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics. ASP-DAC (2017)
Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. ICCAD (2017)
Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam
Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only). FPGA (2017)
Zhe Lin, Wei Zhang, Sharad Sinha
Decision tree based hardware power monitoring for run time dynamic power management in FPGA. FPL (2017)
Ze-ke Wang, Johns Paul, Bingsheng He, Wei Zhang
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 25 (6) (2017)
Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang
PAAS: A system level simulator for heterogeneous computing architectures. FPL (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Yingnan Cui, Wei Zhang, Bingsheng He
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Rakesh Warrier, Wei Zhang, Chan Hua Vun
Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures. Circuits Syst. Signal Process. 36 (9) (2017)
Rakesh Warrier, Shanker Shreejith, Wei Zhang, Chan Hua Vun, Suhaib A. Fahmy
Fracturable DSP Block for Multi-context Reconfigurable Architectures. Circuits Syst. Signal Process. 36 (7) (2017)
Tao Luo, Bingsheng He, Wei Zhang, Douglas L. Maskell
A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography. ICCAD (2017)
Ze-ke Wang, Johns Paul, Hui Yan Cheah, Bingsheng He, Wei Zhang
Relational query processing on OpenCL-based FPGAs. FPL (2016)
Ze-ke Wang, Bingsheng He, Wei Zhang, Shunning Jiang
A performance analysis framework for optimizing OpenCL applications on FPGAs. HPCA (2016)
Sanjeev Das, Wei Zhang, Yang Liu
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Tao Luo, Wei Zhang, Bingsheng He, Douglas L. Maskell
A racetrack memory based in-memory booth multiplier for cryptography application. ASP-DAC (2016)
Bin Zhou, Wei Zhang, Thambipillai Srikanthan, Jason Teo Kian Jin, Vivek Chaturvedi, Tao Luo
Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (5) (2016)
Sanjeev Das, Yang Liu, Wei Zhang, Mahinthan Chandramohan
Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware. IEEE Trans. Inf. Forensics Secur. 11 (2) (2016)
Weichen Liu, Wei Zhang, Xuan Wang, Jiang Xu
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Mohammad Tahghighi, Wei Zhang, Sharad Sinha
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. ISVLSI (2016)
Yingnan Cui, Wei Zhang, Vivek Chaturvedi, Weichen Liu, Bingsheng He
Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme. J. Circuits Syst. Comput. 25 (1) (2016)
Sharad Sinha, Wei Zhang
Low-Power FPGA Design Using Memoization-Based Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Ze-ke Wang, Hui Yan Cheah, Johns Paul, Bingsheng He, Wei Zhang
Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only). FPGA (2016)
Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma
Modular Placement for Interposer based Multi-FPGA Systems. ACM Great Lakes Symposium on VLSI (2016)
Ze-ke Wang, Shuhao Zhang, Bingsheng He, Wei Zhang
Melia: A MapReduce Framework on OpenCL-Based FPGAs. IEEE Trans. Parallel Distributed Syst. 27 (12) (2016)
Mohammad Tahghighi, Sharad Sinha, Wei Zhang
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. ARC (2016)
Yingnan Cui, Wei Zhang, Bingsheng He
A discrete thermal controller for chip-multiprocessors. DATE (2016)
Sanjeev Das, Hao Xiao, Yang Liu, Wei Zhang
Online malware defense using attack behavior model. ISCAS (2016)
Yingnan Cui, Wei Zhang, Vivek Chaturvedi, Bingsheng He
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai (Helen) Li, Bingsheng He
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration. ACM Trans. Design Autom. Electr. Syst. 21 (4) (2016)
Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
HeteroSim: A heterogeneous CPU-FPGA simulator. FPL (2016)
Hao Liang, Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. FPL (2015)
Hao Liang, Yi-Chung Chen, Tao Luo, Wei Zhang, Hai Li, Bingsheng He
Hierarchical Library Based Power Estimator for Versatile FPGAs. MCSoC (2015)
Ze-ke Wang, Bingsheng He, Wei Zhang
Improving Data Partitioning Performance on OpenCL-Based FPGAs. FCCM (2015)
Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li
Hierarchical library based power estimator for versatile FPGAs. FPL (2015)
Ze-ke Wang, Bingsheng He, Wei Zhang
A study of data partitioning on OpenCL-based FPGAs. FPL (2015)
Mengquan Li, Juan Yi, Weichen Liu, Wei Zhang, Lei Yang, Edwin Hsing-Mean Sha
An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era. HPCC/CSS/ICESS (2015)
Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Zhe Wang
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)

Wei Zhang.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Wei Zhang