Tingyuan Liang

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 20

Top Topics

Design Space Exploration

Memory Management

Top Venues

Publications

Ya Wang, Hanwei Fan, Sicheng Li, Tingyuan Liang, Wei Zhang
A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration. DATE (2024)
Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. FPGA (2024)
Weihua Xiao, Shanshan Han, Yue Yang, Shaoze Yang, Cheng Zheng, Jingsong Chen, Tingyuan Liang, Lei Li, Weikang Qian
MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network. ICCAD (2023)
Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. ICFPT (2023)
Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang
PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. DAC (2023)
Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA (2023)
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. CoRR (2022)
Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. CoRR (2022)
Tingyuan Liang, Jingsong Chen, Lei Li, Wei Zhang
AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining. CoRR (2022)
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD (2021)
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL (2020)
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR (2020)
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD (2019)
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA (2019)
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC (2019)
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR (2019)
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE (2019)
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang
PAAS: A system level simulator for heterogeneous computing architectures. FPL (2017)